@article{MTMT:33924701,
	title = {The design of a configurable and low-latency packet parsing system for communication networks},
	url = {https://m2.mtmt.hu/api/publication/33924701},
	author = {Hsu, Kai-Sheng and Shen, Chung-An},
	doi = {10.1007/s11235-023-00992-9},
	journal-iso = {TELECOMMUN SYST},
	journal = {TELECOMMUNICATION SYSTEMS},
	volume = {82},
	unique-id = {33924701},
	issn = {1018-4864},
	abstract = {Parsing is a critical packet processing function in the network node, and the performance and configurability of the packet parsing is essential for designing a low-latency and highly flexible network. This paper presents the VLSI architecture design and circuit implementation of a configurable and low-latency packet parser. The proposed packet parser is based on an instruction architecture to achieve configurability. Furthermore, a novel instruction-reusing scheme is employed in the packet parser so that the instruction-fetch operation is minimized and the latency is reduced. Moreover, in order to reduce size of the required memory, a new structure for the instruction memory is designed where multiple instructions share the same memory location. The proposed packet parser is designed and implemented with a ASIC design flow as well as based on the FPGA platform. Performance evaluations based on the post-layout simulation shows that the proposed packet parser reduces the latency by 30% and the required memory by 70%for the IPv4 and IPv6 protocols.},
	keywords = {Edge Computing; low latency; In-Network Processing; packet parsing},
	year = {2023},
	eissn = {1572-9451},
	pages = {451-463}
}

@inproceedings{MTMT:33372971,
	title = {Fidas: Fortifying the Cloud via Comprehensive FPGA-based Offloading for Intrusion Detection},
	url = {https://m2.mtmt.hu/api/publication/33372971},
	author = {Chen, Jian and Zhang, Xiaoyu and Wang, Tao and Zhang, Ying and Chen, Tao and Chen, Jiajun and Xie, Mingxu and Liu, Qiang},
	booktitle = {PROCEEDINGS OF THE 2022 THE 49TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE (ISCA '22)},
	doi = {10.1145/3470496.3533043},
	unique-id = {33372971},
	abstract = {Network intrusion detection systems (IDS) are crucial for secure cloud computing, but they are also severely constrained by CPU computation capacity as the network bandwidth increases. Therefore, hardware offloading is essential for the IDS servers to support the ever-growing throughput demand for packet processing. Based on the experience of large-scale IDS deployment, we find the existing hardware offloading solutions have fundamental limitations that prevent them from being massively deployed in the production environment. In this paper, we present Fidas, an FPGA-based intrusion detection offload system that avoids the limitations of the existing hardware solutions by comprehensively offloading the primary NIC, rule pattern matching, and traffic flow rate classification. The pattern matching module in Fidas uses a multi-level filter-based approach for efficient regex processing, and the flow rate classification module employs a novel dual-stack memory scheme to identify the hot flows under volumetric attacks. Our evaluation shows that Fidas achieves the state-of-the-art throughput in pattern matching and flow rate classification while freeing up processors for other security-related functionalities. Fidas is deployed in the production data center and has been battle-tested for its performance, cost-effectiveness, and DevOps agility.},
	keywords = {Pattern matching; intrusion detection; balanced offloading; flow rate classification},
	year = {2022},
	pages = {1029-1041}
}

@article{MTMT:33605139,
	title = {Yazılım Tanımlı Radyo Erişim Ağı için Mobil Kullanıcı Türüne Duyarlı Yük Dengeleme Algoritması},
	url = {https://m2.mtmt.hu/api/publication/33605139},
	author = {EREL-OZCEVİK, Muge},
	doi = {10.17798/bitlisfen.1056963},
	journal = {Bitlis Eren Üniversitesi Fen Bilimleri Dergisi},
	volume = {11},
	unique-id = {33605139},
	issn = {2147-3129},
	abstract = {Under extreme increase on video contents in eMBB applications; the 5G requirements cannot been handled by the conventional self-organizing in 4G infrastructure. While executing load balancing in 5G RAN, mobile user type for eMBB applications should be considered. Nowadays, eMBB has been carried by QUIC and HTTP2.0 protocol for Android and iOS users, respectively. In mobile user aware load balancing, Deep Packet Inspection (DPI) up to application layer for packet routing is required. This can be only handled by Software-Defined Network (SDN) without any hardware expenditure in physical infrastructure. Therefore, this paper proposed Software-Defined Radio Access Network (SD-RAN) with two novel functions: Waiting Time Function (WTF) and Load Balancing Function (LBF). In WTF; the queuing inspired approach is proposed for the low complex implementation of the mobile user aware load balancing in 5G-RAN. Waiting Time parameters for iOS and Android users are modeled by M/G/1 and G/G/1 markov queues. It is also executed by M/M/c/K markov model SD-RAN topology. In LBF; a novel Mixed Integer Linear Problem is defined for waiting time optimization. To overcome NP hardness, a local search for the eMBB load threshold analysis is performed and determined as 0.79 and 0.94 for UMas and UMis. A low complex load balancing algorithm is proposed in the light of these thresholds. According to performance results; SD-RAN outperforms nearly 40 % QoS then the conventional SON according to received packet count. It can serve 40\% more user than the conventional one without any extra expenditure on physical infrastructure. As a result, it can handle eMBB flows with acceptable waiting time under 2 milliseconds level.},
	year = {2022},
	pages = {553-563}
}

@CONFERENCE{MTMT:33605123,
	title = {Antennas for 5G and 6G Communications},
	url = {https://m2.mtmt.hu/api/publication/33605123},
	author = {Iffat Naqvi, Syeda and Hussain, Niamat},
	booktitle = {5G and 6G Enhanced Broadband Communications [Working Title]},
	doi = {10.5772/intechopen.105497},
	unique-id = {33605123},
	abstract = {An antenna is of substantial importance for a communication system as the design of an air interface is mainly reliant on the antenna design. With the significant wireless evolution from 1G to 6G, technologies and network capacities are also evolving to fulfill the promptly growing customer demands. These continually increasing demands have gone concurrently with extensive technological accomplishments of the antenna design community. This chapter discusses the sub-6 GHz and millimeter-wave (mm-wave) fifth-generation (5G) antennas, including antenna arrays, multiple-input, multiple-output (MIMO) technology, beam-steering techniques, metasurfaces, and other techniques to achieve the current and impending fast connectivity. Moreover, the design specifications, research directions, various technologies expected to be involved, and challenges in the design, fabrication, and measurement of the sixth-generation (6G) antennas at the THz band have also been presented. In addition, antenna-in-package (AiP) and antenna-on-chip (AoC) technologies with proper technology solutions have also been discussed.},
	year = {2022}
}

@article{MTMT:33243488,
	title = {Efficient pipelined flow classification for intelligent data processing in IoT},
	url = {https://m2.mtmt.hu/api/publication/33243488},
	author = {Mousavi, Seyed Navid and Chen, Fengping and Abbasi, Mahdi and Khosravi, Mohammad R. and Rafiee, Milad},
	doi = {10.1016/j.dcan.2022.04.010},
	journal-iso = {DIGIT COMMUN NETW},
	journal = {DIGITAL COMMUNICATIONS AND NETWORKS},
	volume = {8},
	unique-id = {33243488},
	issn = {2468-5925},
	abstract = {The packet classification is a fundamental process in provisioning security and quality of service for many intelligent network-embedded systems running in the Internet of Things (IoT). In recent years, researchers have tried to develop hardware-based solutions for the classification of Internet packets. Due to higher throughput and shorter delays, these solutions are considered as a major key to improving the quality of services. Most of these efforts have attempted to implement a software algorithm on the FPGA to reduce the processing time and enhance the throughput. The proposed architectures, however, cannot reach a compromise among power consumption, memory usage, and throughput rate. In view of this, the architecture proposed in this paper contains a pipeline -based micro-core that is used in network processors to classify packets. To this end, three architectures have been implemented using the proposed micro-core. The first architecture performs parallel classification based on header fields. The second one classifies packets in a serial manner. The last architecture is the pipeline-based classifier, which can increase performance by nine times. The proposed architectures have been implemented on an FPGA chip. The results are indicative of a reduction in memory usage as well as an increase in speedup and throughput. The architecture has a power consumption of is 1.294w, and its throughput with a frequency of 233 MHz exceeds 147 Gbps.},
	keywords = {EFFICIENCY; pipeline; IoT; packet classification; Intelligent flow processing},
	year = {2022},
	eissn = {2352-8648},
	pages = {561-575},
	orcid-numbers = {Abbasi, Mahdi/0000-0002-5373-5778}
}

@inproceedings{MTMT:33605116,
	title = {HyperParser: A High-Performance Parser Architecture for Next Generation Programmable Switch and SmartNIC},
	url = {https://m2.mtmt.hu/api/publication/33605116},
	author = {Liu, Huan and Qiu, Zhiliang and Pan, Weitao and Li, Jiajun and Huang, Jinjian},
	doi = {10.1145/3469393.3469399},
	unique-id = {33605116},
	year = {2021},
	pages = {50-56}
}

@article{MTMT:31791132,
	title = {Low-Cost and Programmable CRC Implementation Based on FPGA},
	url = {https://m2.mtmt.hu/api/publication/31791132},
	author = {Liu, Huan and Qiu, Zhiliang and Pan, Weitao and Li, Jun and Zheng, Ling and Gao, Ya},
	doi = {10.1109/TCSII.2020.3008932},
	journal-iso = {IEEE T CIRCUITS-II},
	journal = {IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS},
	volume = {68},
	unique-id = {31791132},
	issn = {1549-7747},
	year = {2021},
	eissn = {1558-3791},
	pages = {211-215}
}

@article{MTMT:32403266,
	title = {Architecture design and performance analysis of a novel memory system for high-bandwidth onboard switching fabric},
	url = {https://m2.mtmt.hu/api/publication/32403266},
	author = {Zheng, Ling and Pan, Weitao and Gao, Ya and Liu, Huan and Jiang, Jing},
	doi = {10.1016/j.comnet.2021.108367},
	journal-iso = {COMPUT NETW},
	journal = {COMPUTER NETWORKS},
	volume = {198},
	unique-id = {32403266},
	issn = {1389-1286},
	abstract = {The development of the space-air-ground integration has put higher demands on satellite network. It needs to support high-bandwidth, large-capacity and various quality of service guarantees. However, the satellite onboard switching is facing the problem of resource constraints and special requirements of hardware complexity and scheduling efficiency. For this, this paper proposes a novel memory architecture for high-bandwidth onboard switching fabric. To reduce hardware complexity, multiplexer is used in the input side to merge k input ports into one internal bus, while the output demultiplexer splits an internal bus into k output links. Shared memory architecture is adopted in the input module to improve the memory efficiency, and a buffered crossbar is used to interconnect the input modules to the output modules. A discrete-time queuing model is formulated, and an iterative approach is used to quantitatively analyze the performance of the proposed architecture. The throughput and delay are calculated under different switch size, input load, and buffer capacity. The numerical results can serve as a guidance on deciding the required buffer size and appropriate speedup ratio. This work is validated by both simulations and FPGA implementations. Synthesize result show that using the state-of-the-art Xilinx VU13P FPGA, a switching fabric with 48 ports can be implemented and the peak throughput of the proposed architecture can reach 480 Gbps. Compared with existing combined input-crosspoint queuing, the proposed architecture can significantly reduce the packet delay and the memory resource cost.},
	keywords = {Queuing theory; Satellite network; Onboard switching; Buffered crossbar; Crosspoint-queued switch},
	year = {2021},
	eissn = {1872-7069}
}

@article{MTMT:31681827,
	title = {CRC algorithm for embedded system based on table lookup method},
	url = {https://m2.mtmt.hu/api/publication/31681827},
	author = {Dong, Xiguang and He, Yongqiang},
	doi = {10.1016/j.micpro.2020.103049},
	journal-iso = {MICROPROCESS MICROSY},
	journal = {MICROPROCESSORS AND MICROSYSTEMS},
	volume = {74},
	unique-id = {31681827},
	issn = {0141-9331},
	abstract = {One byte of CRC (Cyclic Redundancy Checks) code is calculated in the general table lookup method each time, and the processing efficiency is not high. Therefore, an improved algorithm based on the general table lookup method is proposed. The improved algorithm processes 2 bytes at a time, that is, calculates a CRC of 2 bytes, and needs to keep the CRC of these 2 bytes separately. After the two-byte information of the next group is input, the CRC of the next two bytes is calculated by using the CRC of the first two bytes. By analogy, the 2-byte CRC code of each group is calculated based on the 2-byte CRC code of the previous group until all information is input. After experimental verification, the results show that the running time of the algorithm is relatively reduced. Aiming at the application of embedded system, based on the analysis of the principle of traditional cyclic redundancy check algorithm, a cyclic redundancy check algorithm based on the look-up table method is proposed to improve the data calibration while ensuring the reliability of the embedded system data. Check the processing speed. (C) 2020 Elsevier B.V. All rights reserved.},
	keywords = {Embedded system; Computer Science, Hardware & Architecture; Computer Science, Theory & Methods; Lookup table method},
	year = {2020},
	eissn = {1872-9436}
}

@article{MTMT:31681828,
	title = {Damage analysis of nano-flexible solid wood composite environmental protection floor on basketball players during training},
	url = {https://m2.mtmt.hu/api/publication/31681828},
	author = {Liu, Haidong and Li, Nana},
	doi = {10.1504/IJNT.2020.110727},
	journal-iso = {INT J NANOTECHNOL},
	journal = {INTERNATIONAL JOURNAL OF NANOTECHNOLOGY},
	volume = {17},
	unique-id = {31681828},
	issn = {1475-7435},
	abstract = {In this research, we investigate and understand the training injuries of basketball players, analyse the factors that cause training injuries, and use polyethylene wood plastic composite single-lap glued joints as the research object. Through different surface treatment methods, bonding processes, and a glueing study on agent performance, bonding strength, stress distribution, and durable failure behaviour of bonding, design single-lap bonding joints, and finally realise seamless connection and bonding joint design of polyethylene wood plastic composites by bonding technology. The rationality of the injury prevention training system was established and applied in basketball, which verified the effectiveness and scientific accuracy of the injury prevention training system. The purpose of this paper is to construct and verify a basketball player training injury system. Based on the existing training system, on the floor made of polyethylene wood plastic composite materials, through practice to effectively design a training program to prevent sports injuries and reduce the incidence of injuries. Lowered to a controllable range, it proves that nano-flexible solid wood composite environmentally friendly flooring can be applied to basketball, which can extend the athlete's sports career to the greatest extent and is committed to improving the athlete's ultimate sports performance.},
	keywords = {LOCATION; NETWORK; Optimization; NANOCOMPOSITE; Nanoscience & Nanotechnology; environmental protection floor; basketball player; training injury},
	year = {2020},
	eissn = {1741-8151},
	pages = {427-441}
}

@article{MTMT:31683686,
	title = {Research and Implementation of a DFA Compression Algorithm with No Matching Time Loss},
	url = {https://m2.mtmt.hu/api/publication/31683686},
	author = {Sun, M.-Q. and Qiao, L.-F. and Chen, Q.-H.},
	doi = {10.3969/j.issn.0372-2112.2020.06.013},
	journal-iso = {TIEN TZU HSUEH PAO / ACTA ELECTRONICA SINICA},
	journal = {TIEN TZU HSUEH PAO / ACTA ELECTRONICA SINICA},
	volume = {48},
	unique-id = {31683686},
	issn = {0372-2112},
	abstract = {Start-of-the-art deep packet inspection system uses deterministic finite automata (DFA) algorithms to perform regular expression matching. Nevertheless, the storage consumption problem caused by DFA make it difficult to apply to FPGA with scarce on-chip resources. At present, there are many algorithms aiming at solving the space explosion problem of DFA, but it affects the detection speed of the system to some extent while bringing better compression ratio. In this paper, a DFA compression algorithm without matching time loss is proposed. Based on the hardware platform of FPGA, a single DFA matching engine is designed and implemented. Experimental results show that the algorithm can achieve a compression rate of 10% to 30% without affecting the matching performance of the whole system. © 2020, Chinese Institute of Electronics. All right reserved.},
	keywords = {Compression rates; FPGA; Field programmable gate arrays (FPGA); Finite automata; Compression algorithms; Hardware platform; DFA; Deterministic finite automata; Deep Packet Inspection; Deep Packet Inspection; Storage compression; Matching engines; Matching performance; Regular-expression matching},
	year = {2020},
	pages = {1132-1139}
}

@inproceedings{MTMT:31790984,
	title = {Microscope: mobile service traffic decomposition for network slicing as a service},
	url = {https://m2.mtmt.hu/api/publication/31790984},
	author = {Zhang, Chaoyun and Fiore, Marco and Ziemlicki, Cezary and Patras, Paul},
	booktitle = {Proceedings of the 26th Annual International Conference on Mobile Computing and Networking},
	doi = {10.1145/3372224.3419195},
	unique-id = {31790984},
	year = {2020},
	pages = {503-516}
}

@CONFERENCE{MTMT:31683687,
	title = {Achieving 100Gbps intrusion prevention on a single server},
	url = {https://m2.mtmt.hu/api/publication/31683687},
	author = {Zhao, Z. and Sadok, H. and Atre, N. and Hoe, J.C. and Sekar, V. and Sherry, J.},
	booktitle = {14th USENIX Symposium on Operating Systems Design and Implementation,OSDI 2020},
	unique-id = {31683687},
	abstract = {Intrusion Detection and Prevention Systems (IDS/IPS) are among the most demanding stateful network functions. Today's network operators are faced with securing 100Gbps networks with 100K+ concurrent connections by deploying IDS/IPSes to search for 10K+ rules concurrently. In this paper we set an ambitious goal: Can we do all of the above in a single server? Through the Pigasus IDS/IPS, we show that this goal is achievable, perhaps for the first time, by building on recent advances in FPGA-capable SmartNICs. Pigasus' design takes an FPGA-first approach, where the majority of processing, and all state and control flow are managed on the FPGA. However, doing so requires careful design of algorithms and data structures to ensure fast common-case performance while densely utilizing system memory resources. Our experiments with a variety of traces show that Pigasus can support 100Gbps using an average of 5 cores and 1 FPGA, using 38× less power than a CPU-only approach. © 2020 Proceedings of the 14th USENIX Symposium on Operating Systems Design and Implementation, OSDI 2020. All rights reserved.},
	keywords = {Systems analysis; Field programmable gate arrays (FPGA); Network security; intrusion detection; Network operator; Integrated circuit design; single server; Network functions; Control flows; Design of algorithms; intrusion prevention; Intrusion detection and prevention systems; System memory},
	year = {2020},
	pages = {1083-1100}
}

@article{MTMT:30699036,
	title = {Computation of Traffic Time Series for Large Populations of IoT Devices},
	url = {https://m2.mtmt.hu/api/publication/30699036},
	author = {Izal, Mikel and Morató, Daniel and Magaña, Eduardo and García-Jiménez, Santiago},
	doi = {10.3390/s19010078},
	journal-iso = {SENSORS-BASEL},
	journal = {SENSORS},
	volume = {19},
	unique-id = {30699036},
	year = {2018},
	eissn = {1424-8220}
}