TY - JOUR AU - Zhang, Zhonghao AU - Li, Zong AU - Yin, Fanghui AU - Cao, Bin AU - Wang, Liming TI - An adaptive Energy acquisition power supply for power transmission line JF - IEICE ELECTRONICS EXPRESS J2 - IEICE ELECTRON EXPR PY - 2023 PG - 6 SN - 1349-2543 DO - 10.1587/elex.20.20230072 UR - https://m2.mtmt.hu/api/publication/33890597 ID - 33890597 AB - Reliable power supply is of great significance to the stable operation of the online monitoring device. This paper studies a kind of electric energy collection power supply based on the principle of current mutual inductance. The iron core is made of nanocrystalline alloy with high permeability, and the relationship between the number of turns and the energy consumption power is analyzed by equivalent circuit. A discharge circuit is formed by connecting multiple diodes in series to avoid oversaturation of the iron core, and the residual voltage on the diode supplies the load electric energy. Combined with simulation and experiment, the number of turns and the number of diodes in series are optimized, so that the power supply has high efficiency and is not easy to be deeply saturated. The rectifier bridge and DC-DC voltage regulator module are used to stabilize the output voltage. The test shows that the power supply can support reliable energy extraction within the range of wire current of 17A at least and 1000A at most, and can be applied to lines of various voltage levels. LA - English DB - MTMT ER - TY - CHAP AU - Kammerer, Jean-Baptiste AU - Garci, Maroua AU - Kaid, Achraf AU - Roqueta, Fabrice ED - Tylman, W TI - Multidomain Modeling for Reliability Evaluation of Devices and Microsystems Using Verilog-A T2 - 2022 29TH INTERNATIONAL CONFERENCE ON MIXED DESIGN OF INTEGRATED CIRCUITS AND SYSTEM (MIXDES 2022) PB - IEEE CY - New York, New York SN - 9788363578220 PY - 2022 SP - 51 EP - 56 PG - 6 DO - 10.23919/MIXDES55591.2022.9838222 UR - https://m2.mtmt.hu/api/publication/33192167 ID - 33192167 LA - English DB - MTMT ER - TY - CHAP AU - Oukaira, Aziz AU - Touati, Djallel Eddine AU - Hassan, Ahmad AU - Ali, Mohamed AU - Savaria, Yvon AU - Lakhssassi, Ahmed ED - Hanaa, Hachimi TI - FEM-based Thermal Profile Prediction for Thermal Management of System-on-Chips T2 - 2022 8th International Conference on Optimization and Applications (ICOA) PB - IEEE CY - Piscataway (NJ) SN - 9781665476812 PY - 2022 SP - 1 EP - 4 PG - 4 DO - 10.1109/ICOA55659.2022.9934719 UR - https://m2.mtmt.hu/api/publication/33632613 ID - 33632613 AB - In this paper, we propose a thermal profile based on the finite element method (FEM). The proposed model is used to predict the temperature profile of the Xilinx™ SPARTAN-3E Field-Programmable Gate Array (FPGA) board during one day. In addition, thermal measurements based on infrared thermography are performed to validate our thermal profiles. These predicted profiles are compared to the temperature maps obtained with a thermal camera over 24 hours. A good agreement, with a maximum error of 1.8 °C, between the predicted and measured temperatures is obtained, which helps a lot in the proper functioning and the thermal management of the system-on-chips (SoC). LA - English DB - MTMT ER - TY - JOUR AU - Saad, Montassar Ben AU - Jedidi, Ahmed AU - Niar, Smail AU - Abid, Mohamed TI - Application source code modification for processor architecture lifetime improvement JF - INTERNATIONAL JOURNAL OF EMBEDDED SYSTEMS J2 - INT J EMBED SYST VL - 11 PY - 2019 IS - 2 SP - 125 SN - 1741-1068 DO - 10.1504/IJES.2019.098289 UR - https://m2.mtmt.hu/api/publication/30723309 ID - 30723309 AB - In the optimal functioning of SoCs, two significant metrics of quality are the most important; lifetime and reliability. The context of this paper focuses on methods to increase the lifetime of a processor. Two methods are presented: relax point injection (RPI) and code structure adaptation (CSA). In RPI, a specific treatment is incorporated into the application code to prevent a harmful rise in the temperature of the chip. The MTTF of the processor is increased by 33.88% through means of an RPI method. However, the execution time of the application is sometimes increased by the RPI to a higher than 12%. In CSA method, the arrangement of the application code is regulated to improve the lifetime of the processor. The MTTF of the processor is increased up to 28% by CSA technique and the implementation time is maintained. LA - English DB - MTMT ER - TY - JOUR AU - Németh, Márton AU - Takács, Gábor AU - Jani, Lázár AU - Poppe, András TI - Compact modeling approach for microchannel cooling and its validation JF - MICROSYSTEM TECHNOLOGIES J2 - MICROSYST TECHNOL VL - 24 PY - 2018 IS - 1 SP - 419 EP - 431 PG - 13 SN - 0946-7076 DO - 10.1007/s00542-017-3330-z UR - https://m2.mtmt.hu/api/publication/3157075 ID - 3157075 N1 - Cited By :4 Export Date: 28 September 2022 Correspondence Address: Németh, M.; Department of Electron Devices, Magyar tudósok krt. 2, Bldg. Q, wing B, 3rd floor, Hungary; email: nemeth@eet.bme.hu LA - English DB - MTMT ER - TY - CHAP AU - Jani, Lázár AU - Poppe, András ED - Paul, Wesling TI - Extending a Multi-Level Logi-Thermal Simulation Framework to a Mixed Signal Thermal Aware Simulation Environment Using SystemC-AMS T2 - 2017 16th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm) PB - IEEE CY - Danvers (MA) SN - 9781467381208 PY - 2017 SP - 307 EP - 313 PG - 8 DO - 10.1109/ITHERM.2017.7992486 UR - https://m2.mtmt.hu/api/publication/3237362 ID - 3237362 AB - With the advance of the semiconductor technology power density and related thermal management issues became design bottlenecks. These physical limits require design engineers to make several thermal aware decisions during the design process: the earlier the better. Modern hardware description languages have extensions for simulation of mixed-signal circuits (e.g. SystemC-AMS, Verilog-AMS, VHDL-AMS) but none of these approaches support co-simulation of the effect of the foreseen thermal environment of the design with the logic behavior. A relatively new simulation paradigm called logithermal simulation is aimed to fill this gap in the available set of simulation tools. Our framework for co-simulation of logic and thermal behavior called LogiTherm contains generic interfaces towards usual logic and thermal simulation engines. In our present framework setup SystemC and Verilog is supported as hardware description languages and two thermal field solvers, SUNRED and 3D-ICE can be used as thermal simulation engines. In this paper we present the recent developments of the LogiTherm framework that enable logithermal simulation of mixed signal designs. We demonstrate the capability of our system by presenting simulation results of a test system, which contains a microprocessor and mixed signal components as well. LA - English DB - MTMT ER - TY - JOUR AU - Jani, Lázár AU - Poppe, András TI - Framework for thermal-aware verification of digital and mixed signal systems JF - MICROELECTRONICS RELIABILITY J2 - MICROELECTRON RELIAB VL - 79 PY - 2017 SP - 499 EP - 508 PG - 12 SN - 0026-2714 DO - 10.1016/j.microrel.2017.03.023 UR - https://m2.mtmt.hu/api/publication/3207234 ID - 3207234 N1 - Közlemény azonosító:MR12323 LA - English DB - MTMT ER - TY - JOUR AU - Zheng, Wang AU - Shazia, Kanwal AU - Lai, Wang AU - Anupam, Chattopadhyay TI - Automated High-level Modeling of Power, Temperature and Timing Variation for Microprocessor JF - KMUTNB INTERNATIONAL JOURNAL OF APPLIED SCIENCE AND TECHNOLOGY J2 - KMUTNB IJAST VL - 2017 PY - 2017 IS - Aug PG - 13 DO - 10.14416/j.ijast.2017.08.002 UR - https://m2.mtmt.hu/api/publication/26783844 ID - 26783844 LA - English DB - MTMT ER - TY - JOUR AU - Brunner, D AU - Burke, W AU - Kuang, A Q AU - LaBombard, B AU - Lipschultz, B AU - Wolfe, S TI - Feedback system for divertor impurity seeding based on real-time measurements of surface heat flux in the Alcator C-Mod tokamak JF - REVIEW OF SCIENTIFIC INSTRUMENTS J2 - REV SCI INSTRUM VL - 87 PY - 2016 IS - New York PG - 7 SN - 0034-6748 DO - 10.1063/1.4941047 UR - https://m2.mtmt.hu/api/publication/25796311 ID - 25796311 N1 - Plasma Science and Fusion Center, Massachusetts Institute of Technology, Cambridge, MA 02139, United States Department of Physics, University of York, Heslington, York, YO10 5DD, United Kingdom Cited By :18 Export Date: 16 November 2021 CODEN: RSINA LA - English DB - MTMT ER - TY - CHAP AU - Jani, Lázár AU - Poppe, András ED - Poppe, András TI - Improved Method for Logi-Thermal Simulation with Temperature Dependent Signal Delay T2 - 2016 22nd International Workshop on THERMal INvestigation of ICs and Systems (THERMINIC'16) PB - IEEE CY - New York, New York SN - 9781509054503 PY - 2016 SP - 302 EP - 306 PG - 5 DO - 10.1109/THERMINIC.2016.7749071 UR - https://m2.mtmt.hu/api/publication/3115614 ID - 3115614 N1 - Befoglaló mű WoS és MTMT megnevezése nem azonos. Az MTMT-ben 1995 óta standardizált konferenciamegnevezéssel lett a befoglaló mű rögzítve. AB - Evolution of the semiconductor manufacturing allows integrating more components on a single die which further increase the complexity of the chips and introduce new design challenges. Power dissipation density has reached the limits of current cooling solutions, thus thermal-aware decisions must be taken into account during the design process. Co-simulating the logic function and thermal behaviour of the design can help to evaluate the performance of the system at various stages of the design process. Logi-thermal simulators use the switching activities of the system to predict the dissipated power and calculate the temperature distribution across the chip. The temperature dependence of certain parameters (such as delay) can also be considered during the co-simulation. This paper presents an improved method for temperature dependent signal delays compared to previous solutions. Our approach is based on mixed abstraction level logic simulation, which reduce the simulation time while the temperature distribution and the calculated delays remain accurate. LA - English DB - MTMT ER - TY - JOUR AU - Jani, Lázár AU - Poppe, András TI - Multilevel logic and thermal co-simulation JF - MICROELECTRONICS RELIABILITY J2 - MICROELECTRON RELIAB VL - 67 PY - 2016 IS - 12 SP - 46 EP - 53 PG - 8 SN - 0026-2714 DO - 10.1016/j.microrel.2016.08.019 UR - https://m2.mtmt.hu/api/publication/3106711 ID - 3106711 AB - While the semiconductor industry makes progress in every year integrating more components on a single die and stacking them, manufacturers face great challenge as the dissipated power densities reach the limits of current cooling solutions. Since peak temperature and temperature gradients influence the functional behavior of the ICs, co-simulation of the logic function and thermal behavior can help to assess the overall performance of the system at various stages of the design flow better. Logi-thermal simulators (extending the concept of the transistor level electro-thermal simulation of integrated circuits to higher abstraction levels) can predict the dissipated power based on the switching activities of the system, consider the local temperature dependence of certain circuit properties and calculate the temperature distribution across the chip consistently. This paper presents a logi-thermal simulation framework that allows to couple logic simulators and thermal solver engines to facilitate the co-simulation of high level functional and thermal behavior of digital circuits, both on gate level and register-transfer level. We show examples by integrating SystemC with the thermal simulator SUNRED, and comparing the results of a gate level logi-thermal simulation and logi-thermal simulation obtained with the register-transfer level description of the same system. LA - English DB - MTMT ER - TY - CHAP AU - Németh, Márton AU - Jani, Lázár AU - Poppe, András ED - B, Charlot ED - Y, Mita ED - P, Nouet ED - F, Pressecq ED - Kerecsen Istvánné Rencz, Márta ED - P, Schneider ED - N, Tas TI - Compact modeling approach for microchannel cooling aimed at high-level thermal analysis of 3D packaged ICs T2 - Proceedings of the Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP'16) PB - IEEE CY - New York, New York SN - 9781509015054 PY - 2016 SP - 182 EP - 187 PG - 6 DO - 10.1109/DTIP.2016.7514865 UR - https://m2.mtmt.hu/api/publication/3064883 ID - 3064883 AB - This paper presents a new compact modeling technique to describe the convective heat transfer realized by a flow of coolant in integrated microchannels used for thermal management of IC chips. This model works only in case of laminar flow and straight microchannels. The compact model represents the convective heat transfer with alternating resistors in the flow path. The implementation of this model in a successive node reduction (SUNRED) algorithm based thermal filed solver is also presented. A simulation example for a simplified geometry with one channel situated in the center of a pyramidal stack of silicon dice is presented, though, the final target application is in the thermal simulation engine of a logi-thermal simulation system. The errors have been calculated as the difference of the results of the alternating resistor and modified SUNRED model and the result of a detailed CFD simulation. The error of our new compact model was below 2 % for both modeling techniques. LA - English DB - MTMT ER - TY - JOUR AU - Poppe, András TI - Multi-domain compact modeling of LEDs: an overview of models and experimental data JF - MICROELECTRONICS JOURNAL J2 - MICROELECTRON J VL - 46 PY - 2015 IS - 12 A SP - 1138 EP - 1151 PG - 14 SN - 0026-2692 DO - 10.1016/j.mejo.2015.09.013 UR - https://m2.mtmt.hu/api/publication/2946363 ID - 2946363 N1 - Megjegyzés-25412367 Megjegyzés-26507359 PN A AB - Operating parameters of power LEDs are strongly coupled and are mutually dependent. There have been lots of attempts to provide different kinds of multi-domain LED models with different complexity. This paper gives an overview of recently published models and suggests a practical approach in which the forward current is split into two parts in a straightforward manner. One current component is derived from the LED’s measured radiant flux directly, the other component is calculated as the difference of the net forward current and the previously mentioned current component associated with light emission. Parameters of the proposed model can be identified from isothermal LED characteristics measured in industry standard LED test setups using textbook techniques. Temperature dependence of the model parameters is discussed in detail; including comparison of different models for the temperature dependence of the saturation current in Shockley’s diode equation. LA - English DB - MTMT ER - TY - JOUR AU - Garci, Maroua AU - Kammerer, Jean-Baptiste AU - Hebrard, Luc TI - Towards electro-thermo-mechanical simulation of integrated circuits in standard CAD environment JF - MICROELECTRONICS JOURNAL J2 - MICROELECTRON J VL - 46 PY - 2015 IS - 12 SP - 1121 EP - 1128 PG - 8 SN - 0026-2692 DO - 10.1016/j.mejo.2015.09.006 UR - https://m2.mtmt.hu/api/publication/25570744 ID - 25570744 LA - English DB - MTMT ER - TY - JOUR AU - Nagy, Gergely AU - Horváth, Péter AU - Pohl, László AU - Poppe, András TI - Advancing the thermal stability of 3D ICs using logi-thermal simulation JF - MICROELECTRONICS JOURNAL J2 - MICROELECTRON J VL - 46 PY - 2015 IS - 12, Part: A SP - 1114 EP - 1120 PG - 7 SN - 0026-2692 DO - 10.1016/j.mejo.2015.06.025 UR - https://m2.mtmt.hu/api/publication/2908301 ID - 2908301 N1 - Megjegyzés-25412368 Megjegyzés-26505942 PN A Issue: 12, Part: A WoS:hiba:000367859500003 2020-08-29 08:48 füzet nem egyezik LA - English DB - MTMT ER - TY - JOUR AU - Igić, Petar TI - Exponential ADE Solution Based Compact Model of Planar Injection Enhanced IGBT Dedicated to Robust Power Converter Design JF - IEEE TRANSACTIONS ON POWER ELECTRONICS J2 - IEEE T POWER ELECTR VL - 30 PY - 2015 IS - 4 SP - 1914 EP - 1924 PG - 11 SN - 0885-8993 DO - 10.1109/TPEL.2014.2330655 UR - https://m2.mtmt.hu/api/publication/24233195 ID - 24233195 AB - The compact model of an injection enhanced insulated gate bipolar transistors based on the exponential solution of the ambipolar diffusion equation is presented in this paper. To model plasma carrier distribution, an exponential shape function is used, and in steady-state forward bias operation, the plasma carrier concentration has a distribution of catenary form with just two exponential basis functions, while in transient operation, more complex profiles can be approximated using a number of exponential basis functions with a range of decay length parameters, shorter than the steady state ones. The device model developed has been implemented in Saber circuit simulator and successfully tested against complete set of high current, high voltage experimental results. LA - English DB - MTMT ER - TY - CONF AU - Yu, Cheng Guicui Fu TI - A physics-based electro-thermal model for FS IGBT T2 - The 2015 3rd International Conference on Material, Mechanical and Manufacturing Engineering (IC3ME 2015) PB - Atlantis Press PB - Atlantis Press PY - 2015 SP - 1107 EP - 1111 UR - https://m2.mtmt.hu/api/publication/25281927 ID - 25281927 LA - English DB - MTMT ER - TY - THES AU - Nadereh, Hatami Mazinani TI - Multi-Level Analysis of Non-Functional Properties PY - 2014 SP - 210 UR - https://m2.mtmt.hu/api/publication/23892243 ID - 23892243 N1 - Von der Fakultaet Informatik, Elektrotechnik und Informationstechnik der Universitaet Stuttgart zur Erlangung der Würde eines Doktors der Naturwissenschaften (Dr. rer. nat.) Institut für Technische Informatik der Universitaet Stuttgart http://elib.uni-stuttgart.de/opus/volltexte/2014/9230/ LA - English DB - MTMT ER - TY - JOUR AU - Petar, Igić AU - Nebojša, Janković TI - REVIEW OF ADVANCED IGBT COMPACT MODELS DEDICATED TO CIRCUIT SIMULATION JF - FACTA UNIVERSITATIS SERIES: ELECTRONICS AND ENERGETICS J2 - FACTA UNIV SER ELECTRON ENERGET VL - 27 PY - 2014 IS - 1 SP - 13 EP - 23 PG - 11 SN - 0353-3670 DO - 10.2298/FUEE1401013I UR - https://m2.mtmt.hu/api/publication/23892244 ID - 23892244 AB - The paper aims to review the research area of the IGBT compact modelling and to introduce different device models. The models are separated in two groups, one that solves ambipolar diffusion equation (ADE) and one that does not. Both types of compact models have been successfully used in the past for power electronic circuit design. LA - English DB - MTMT ER - TY - CHAP AU - Petrosyants, K O AU - Rjabov, N I TI - Logi-thermal analysis of digital circuits using mixed-signal simulator Questa ADMS T2 - East-West Design & Test Symposium, 2013 SN - 9781479920952 PY - 2013 SP - 1 EP - 4 PG - 4 DO - 10.1109/EWDTS.2013.6673151 UR - https://m2.mtmt.hu/api/publication/23892242 ID - 23892242 LA - English DB - MTMT ER - TY - JOUR AU - Save, YD AU - Narayanan, H AU - Patkar, SB TI - Solution of PDEs-electrically coupled systems with electrical analogy JF - INTEGRATION-THE VLSI JOURNAL J2 - INTEGRATION-VLSI J VL - 46 PY - 2013 IS - 4 SP - 427 EP - 440 PG - 14 SN - 0167-9260 DO - 10.1016/j.vlsi.2012.10.002 UR - https://m2.mtmt.hu/api/publication/23892241 ID - 23892241 LA - English DB - MTMT ER - TY - THES AU - Timár, András TI - Logi-termikus szimuláció sztenderd tervező rendszerekben PB - Budapesti Műszaki és Gazdaságtudományi Egyetem PY - 2013 UR - https://m2.mtmt.hu/api/publication/2944137 ID - 2944137 N1 - Megjegyzés-25283808 Budapesti M˝uszaki és Gazdaságtudományi Egyetem Villamosmérnöki és Informatikai Kar Elektronikus Eszközök Tanszéke Megjegyzés-25283815 Budapesti Műszaki és Gazdaságtudományi Egyetem Villamosmérnöki és Informatikai Kar Elektronikus Eszközök Tanszéke LA - Hungarian DB - MTMT ER - TY - JOUR AU - Chen, JQ AU - Chen, X AU - Liu, CJ AU - Huang, KM AU - Xu, XB TI - Analysis of Temperature Effect on p-i-n Diode Circuits by a Multiphysics and Circuit Cosimulation Algorithm JF - IEEE TRANSACTIONS ON ELECTRON DEVICES J2 - IEEE T ELECTRON DEV VL - 59 PY - 2012 IS - 11 SP - 3069 EP - 3077 PG - 9 SN - 0018-9383 DO - 10.1109/TED.2012.2211602 UR - https://m2.mtmt.hu/api/publication/23892233 ID - 23892233 LA - English DB - MTMT ER - TY - CHAP AU - Nagy, Gergely AU - Timár, András AU - Szalai, Albin AU - Kerecsen Istvánné Rencz, Márta AU - Poppe, András ED - Paul, Wesling ED - Kathe, Ericson TI - New simulation approaches supporting temperature-aware design of digital ICs T2 - 2012 28th Annual IEEE Semiconductor Thermal Measurement and Management Symposium (SEMI-THERM) PB - IEEE CY - New York, New York SN - 9781467311113 T3 - PROCEEDINGS, IEEE SEMICONDUCTOR THERMAL MEASUREMENT AND MANAGEMENTSYMPOSIUM, ISSN 1065-2221 PY - 2012 SP - 313 EP - 318 PG - 6 DO - 10.1109/STHERM.2012.6188866 UR - https://m2.mtmt.hu/api/publication/2683177 ID - 2683177 AB - Regarding thermal issues in digital IC design a major concern is how timing integrity is affected by the elevated junction temperature and temperature gradients on the chip surface. To predict this in a thermal aware design process one needs a dedicated simulation tool in which the logic simulation of the circuit is coupled to the thermal simulation of the chip and its environment. This paper presents two approaches to this so called logi-thermal simulation. In one of our approaches we rely completely on industry standard EDA tools, standard EDA file formats and interfaces. In the other solution which provides us total freedom in the abstraction level of circuit description and simulation accuracy we use our own logic simulation engine. In both cases the logic simulation engine is connected to our own thermal simulation engines which also use compact thermal models of the IC package during simulation. This paper describes certain implementation aspects and features of our logi-thermal simulation solutions, with emphasizes on modeling the thermal properties of the IC packaging. LA - English DB - MTMT ER - TY - CHAP AU - Timár, András AU - Kerecsen Istvánné Rencz, Márta ED - IEEE, null TI - Studying the influence of chip temperatures on timing integrity T2 - Proceedings of the 12th IEEE Latin-American Test Workshop (LATW'11) PB - IEEE Press CY - New York, New York SN - 9781457714894 PY - 2011 PG - 5 DO - 10.1109/LATW.2011.5985920 UR - https://m2.mtmt.hu/api/publication/2662891 ID - 2662891 AB - Thermal (side-)effects can detrimentally influence operation of integrated circuits. The increase of temperature changes the devices’ characteristics and may result in timing integrity issues. In extreme cases the increased delays can foil correct operation of the circuit. This paper presents a methodology as well as a tool to address timing integrity errors caused by thermal effects. The methodology presented shows how the thermal distribution map on the IC surface can be used to calculate device delay changes during logic simulation. A software tool called CellTherm developed in the Department of Electron Devices, BME, Hungary is also briefly presented in this paper. With the help of the software, logic simulations of digital integrated circuits can be back-annotated with temperaturedependent delays during the running simulation. LA - English DB - MTMT ER - TY - JOUR AU - Chen, M AU - Hu, A AU - Tang, Y AU - Wang, B TI - SABER-based simulation for compact dynamic electro-thermal modeling analysis of power electronic devices JF - ADVANCED MATERIALS RESEARCH J2 - ADV MATER RES VL - 291-294 PY - 2011 SP - 1704 EP - 1708 PG - 5 SN - 1022-6680 DO - 10.4028/www.scientific.net/AMR.291-294.1704 UR - https://m2.mtmt.hu/api/publication/23892227 ID - 23892227 LA - English DB - MTMT ER - TY - CHAP AU - Nagy, Gergely AU - Poppe, András ED - Bernard, Courtois ED - Marta, Rencz TI - A Novel Simulation Environment Enabling Multilevel Power Estimation of Digital Systems T2 - Proceedings of the 17th International Workshop on THERMal INvestigation of ICs and Systems (THERMINIC'11) PB - EDA Publishing Association CY - Grenoble SN - 9781457707780 PY - 2011 SP - 149 EP - 152 PG - 4 UR - https://m2.mtmt.hu/api/publication/2668280 ID - 2668280 AB - This paper presents a novel logi-thermal simulator architecture. A logi-thermal simulator encorporates a logic and a thermal core in strong coupling. It is capable of calculating the self-heating of digital blocks and is able to account for the consequences of temperature change by implementing the delays of the blocks as a function of the temperature. The simulator architecture presented is able to work with logic entities described at different levels of abstraction. This allows to simulate a design at a very early phase when only high-level descriptions are available or to simulate systems that have elements in different design phases. Such a feature enables engineers to perform logi-thermal simulation throughout almost the entire design process which allows for the application of multiple-level optimization. It can also be used to shorten simulation times when only some parts of the design need to be simulated in high detail. LA - English DB - MTMT ER - TY - CHAP AU - Krencker, J -C AU - Kammerer, J -B AU - Hervé, Y AU - Hébrard, L ED - Bernard, Courtois ED - Marta, Rencz TI - 3D electro-thermal simulations of analog ICs carried out with standard CAD tools and verilog-A T2 - Proceedings of the 17th International Workshop on THERMal INvestigation of ICs and Systems (THERMINIC'11) PB - EDA Publishing Association CY - Grenoble SN - 9781457707780 PY - 2011 SP - 19 EP - 22 PG - 4 UR - https://m2.mtmt.hu/api/publication/23893013 ID - 23893013 LA - English DB - MTMT ER - TY - THES AU - Theodore, Robert HARRIS TI - Electrothermal Analysis of Three-Dimensional Integrated Circuits PY - 2011 SP - 197 UR - https://m2.mtmt.hu/api/publication/23892237 ID - 23892237 N1 - North Carolina State University, Ann Arbor USA ISBN: 9781124753263 Dissertation/thesis number 3463771 ProQuest document ID 881294103 LA - English DB - MTMT ER - TY - CHAP AU - Timár, András AU - Bognár, György AU - Poppe, András AU - Kerecsen Istvánné Rencz, Márta ED - Bernard, Courtois ED - Kerecsen Istvánné Rencz, Márta TI - Electro-thermal co-simulation of ICs with runtime back-annotation capability T2 - Proceedings of the 16th International Workshop on THERMal INvestigation of ICs and Systems (THERMINIC'10) PB - IEEE CY - Barcelona SN - 9782355000126 PY - 2010 SP - 183 EP - 188 PG - 6 UR - https://m2.mtmt.hu/api/publication/2655080 ID - 2655080 AB - This paper presents a novel approach to logical and thermal co-simulation of ASIC circuits. Numerous electrothermal simulator implementations are present nowadays, but these simulators approach the electro-thermal simulation domain by co-simulating electronic and thermal effects at a low structural level. This approach has the advantage of being very accurate but at the expense of simulation time. In this paper we provide an alternative way to simulate standard cell ASIC circuits electrically and thermally in a concurrent process in real-time, in RTL level. Our approach takes standard cells of the digital design as basic building blocks and calculates a thermal distribution map on the surface of the virtual chip. The temperature map is calculated from the cells’ power characteristics and the switching activity of the regularly working circuit. We call the presented approach logi-thermal simulation. An implementation of the method is also presented in this paper: a new simulation software, LogiTherm is under heavy development in the Department of Electron Devices at BME, Hungary. LA - English DB - MTMT ER - TY - CHAP AU - Culpo, M AU - de Falco, C AU - Denk, G AU - Voigtmann, S TI - Automatic Thermal Network Extraction and Multiscale Electro-Thermal Simulation T2 - SCIENTIFIC COMPUTING IN ELECTRICAL ENGINEERING SCEE 2008 SN - 9783642122934 T3 - Mathematics in Industry ; 14. PY - 2010 SP - 281 EP - 288 PG - 8 DO - 10.1007/978-3-642-12294-1_36 UR - https://m2.mtmt.hu/api/publication/23892210 ID - 23892210 LA - English DB - MTMT ER - TY - CHAP AU - J, Ch Krencker AU - J B, Kammerer AU - Y, Hervé AU - L, Hébrard ED - Bernard, Courtois ED - Kerecsen Istvánné Rencz, Márta TI - Direct Electro-Thermal Simulation of Integrated Circuits using Standard CAD Tools T2 - Proceedings of the 16th International Workshop on THERMal INvestigation of ICs and Systems (THERMINIC'10) PB - IEEE CY - Barcelona SN - 9782355000126 PY - 2010 SP - 61 EP - 64 PG - 4 UR - https://m2.mtmt.hu/api/publication/23892209 ID - 23892209 LA - English DB - MTMT ER - TY - CHAP AU - Timár, András AU - Poppe, András AU - Kerecsen Istvánné Rencz, Márta ED - Napieralski, Andrzej TI - A Novel Approach of Logi-thermal Simulation Methodology and Implementation for ASIC Designs T2 - Proceedings of the 17th International Conference Mixed Design of Integrated Circuits and Systems (MIXDES '10) PB - IEEE Press CY - Piscataway (NJ) SN - 9788392875635 PY - 2010 SP - 351 EP - 356 PG - 6 UR - https://m2.mtmt.hu/api/publication/2662675 ID - 2662675 LA - English DB - MTMT ER - TY - THES AU - Karthik, Sankaranarayanan TI - Thermal Modeling and Management of Microprocessors PY - 2009 SP - 158 UR - https://m2.mtmt.hu/api/publication/23932525 ID - 23932525 N1 - A Dissertation Presented to the faculty of the School of Engineering and Applied Science, University of Virginia; In Partial Fulfillment of the requirements for the Degree Doctor of Philosophy in Computer Science LA - English DB - MTMT ER - TY - CHAP AU - Klab, S AU - Napieralski, A AU - De Mey, G TI - Logi-Thermal Simulation of Digital CMOS ICs with Emphasis on Dynamic Power Dissipation T2 - MIXDES 2009: PROCEEDINGS OF THE 16TH INTERNATIONAL CONFERENCE MIXED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS SN - 9788392875604 PY - 2009 SP - 361 EP - 365 PG - 5 UR - https://m2.mtmt.hu/api/publication/23892211 ID - 23892211 LA - English DB - MTMT ER - TY - THES AU - Massimiliano, Culpo TI - Numerical Algorithms for System Level Electro-Thermal Simulation PY - 2009 UR - https://m2.mtmt.hu/api/publication/23892236 ID - 23892236 N1 - Bergische Universitaet Wuppertal, Fachbereich Mathematik und Naturwissenschaften, Lehrstuhl für Angewandte Mathematik und Numerische Mathematik LA - English DB - MTMT ER - TY - CHAP AU - Petrosjanc, KO AU - Ryabov, NI AU - Kharitonov, IA AU - Kozynko, PA ED - anon, , TI - Electro-thermal simulation: A new subsystem in mentor graphics IC design flow T2 - Proceedings of the 15th International Worshop on THERMal INvestigations of ICs and Systems (THERMINIC'09) PB - EDA Publishing Association CY - Grenoble SN - 9782355000102 PB - Institute of Electrical and Electronics Engineers (IEEE) PY - 2009 SP - 70 EP - 74 PG - 5 UR - https://m2.mtmt.hu/api/publication/26443868 ID - 26443868 LA - English DB - MTMT ER - TY - CHAP AU - Poppe, András AU - Horváth, György Gábor AU - Nagy, Gergely AU - Kerecsen Istvánné Rencz, Márta AU - Székely, Vladimir ED - Wesling, P ED - Erickson, K TI - Electro-thermal and logi-thermal simulators aimed at the temperature-aware design of complex integrated circuits T2 - Proceedings of the 24th IEEE Semiconductor Thermal Measurement and Management Symposium (SEMI-THERM'08) PB - IEEE CY - New York, New York SN - 9781424421237 PY - 2008 SP - 68 EP - 76 PG - 9 DO - 10.1109/STHERM.2008.4509369 UR - https://m2.mtmt.hu/api/publication/2613659 ID - 2613659 LA - English DB - MTMT ER - TY - JOUR AU - Brian, Swahn AU - Soha, Hassoun TI - Electro-Thermal Analysis of Multi-Fin Devices JF - IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS J2 - IEEE T VLSI SYST VL - 16 PY - 2008 IS - 7 SP - 816 EP - 829 PG - 14 SN - 1063-8210 DO - 10.1109/TVLSI.2008.2000455 UR - https://m2.mtmt.hu/api/publication/23892205 ID - 23892205 N1 - DOI: 10.1109/TVLSI.2008.2000455 Megjegyzés-23932591 DOI: 10.1109/TVLSI.2008.2000455 LA - English DB - MTMT ER - TY - JOUR AU - Etessam-Yazdani, K AU - Asheghi, M AU - Hamann, H F TI - Investigation of the Impact of Power Granularity on Chip Thermal Modeling Using White Noise Analysis JF - IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES J2 - IEEE T COMPON PACK T VL - 31 PY - 2008 IS - 1 SP - 211 EP - 215 PG - 5 SN - 1521-3331 DO - 10.1109/TCAPT.2008.916859 UR - https://m2.mtmt.hu/api/publication/23892202 ID - 23892202 N1 - doi:10.1109/TCAPT.2008.916859 Megjegyzés-23892528 doi:10.1109/TCAPT.2008.916859 Megjegyzés-23932598 doi:10.1109/TCAPT.2008.916859 LA - English DB - MTMT ER - TY - CHAP AU - Nagy, Gergely AU - Horváth, György Gábor AU - Poppe, András ED - IEEE, null TI - Consideration of Thermal Effects in Logic Simulation T2 - Proceedings of the 14th International Workshop on THERMal INvestigation of ICs and Systems (THERMINIC'08) PB - EDA Publishing Association CY - Grenoble SN - 9782355000089 PY - 2008 SP - 229 EP - 234 PG - 6 DO - 10.1109/THERMINIC.2008.4669914 UR - https://m2.mtmt.hu/api/publication/2626538 ID - 2626538 AB - This paper presents a method that considers thermal effects in logic simulations. The aim is to develop a tool that is capable of modeling the thermal behavior of a digital circuit and, at the same time, yields results almost at the speed of ordinary logic simulators. The importance of such a simulation is that thermal effects can be the cause of signal integrity problems. The structure and the basic operation of the simulator are discussed as well as the issues that need to be addressed throughout the development. A detailed description of the implementation of the tightly integrated thermal and logic simulation is also given. LA - English DB - MTMT ER - TY - JOUR AU - Mohammadi, F A AU - Attar, S Sharifian TI - Development of an electrothermal simulation tool for integrated circuits: Application to a two-transistor circuit JF - CANADIAN JOURNAL OF ELECTRICAL AND COMPUTER ENGINEERING-REVUE CANADIENNE DE GENIE ELECTRIQUE ET INFORMATIQUE J2 - CAN J ELECT COMPUT E VL - 33 PY - 2008 IS - Niagara Falls SP - 191 EP - 200 PG - 10 SN - 0840-8688 DO - 10.1109/CJECE.2008.4721625 UR - https://m2.mtmt.hu/api/publication/26436502 ID - 26436502 LA - English DB - MTMT ER - TY - CONF AU - Petrosjanc, KO AU - Rjabov, NI AU - Kharitonov, IA AU - Kozunko, P TI - Realizacija processaelektro teplovogo modelirovanija v SAPR BIS Mentor Graphics [Реализация процесса электротеплового моделирования в САПР БИС Mentor Graphics] T2 - Problemi razrabotki mikro- i nanoelektronnikh sistem – 2008 Sbornik nauchnikh trudov [Проблемы разработки перспективных микро- и наноэлектронных систем - 2008. Сборник научных трудов / под общ. ред. А.Л.Стемпковского. М.:ИППМ РАН,] PY - 2008 SP - 243 EP - 246 PG - 4 UR - https://m2.mtmt.hu/api/publication/23892239 ID - 23892239 LA - Russian DB - MTMT ER - TY - CHAP AU - Xu, L AU - Lindfors, S AU - Ryynänen, J TI - An ADPLL-based fast start-up technique for sensor radio frequency synthesizers T2 - Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008 SN - 9781424421824 PY - 2008 SP - 388 EP - 391 PG - 4 DO - 10.1109/ICECS.2008.4674872 UR - https://m2.mtmt.hu/api/publication/23892231 ID - 23892231 LA - English DB - MTMT ER - TY - CHAP AU - Attar, S S AU - Yagoub, M C E AU - Mohammadi, F TI - New Electro-Thermal Integrated Circuit Modeling using Coupling of Simulators T2 - Proceedings of the Canadian Conference on Electrical and Computer Engineering (CCECE'06) SN - 1424400384 PY - 2007 SP - 1218 EP - 1222 PG - 5 DO - 10.1109/CCECE.2006.277791 UR - https://m2.mtmt.hu/api/publication/23892188 ID - 23892188 LA - English DB - MTMT ER - TY - CONF AU - Keiji, Nakabayashi AU - Kazuo, Nakajima AU - Hajimu, Iida TI - A New Technique of Multi-layer Thermal Analysis for VLSI Chips T2 - Proceedings of the 9th WSEAS Int. Conference on Mathematical Methods and Computational Techniques in Electrical Engineering PY - 2007 SP - 24 EP - 30 PG - 7 UR - https://m2.mtmt.hu/api/publication/23892207 ID - 23892207 LA - English DB - MTMT ER - TY - GEN AU - N, Nelson AU - G, Briggs AU - M, Haurylau AU - G, Chen AU - H, Chen AU - D H, Albonesi AU - E G, Friedman AU - P M, Fauchet TI - Alleviating Thermal Constraints while Maintaining Performance Via Silicon-Based On-Chip Optical Interconnects PY - 2007 UR - https://m2.mtmt.hu/api/publication/23892197 ID - 23892197 LA - English DB - MTMT ER - TY - CHAP AU - Poppe, András AU - Farkas, Gábor AU - Székely, Vladimir AU - Horváth, György Gábor AU - Kerecsen Istvánné Rencz, Márta ED - Wesling, P ED - Erickson, K TI - Multi-domain simulation and measurement of power LED-s and power LED assemblies T2 - Proceedings of the 22nd IEEE Semiconductor Thermal Measurement and Management Symposium (SEMI-THERM'06) PB - IEEE CY - New York, New York SN - 9781424401536 PY - 2006 SP - 191 EP - 198 PG - 8 DO - 10.1109/STHERM.2006.1625227 UR - https://m2.mtmt.hu/api/publication/2613643 ID - 2613643 LA - English DB - MTMT ER - TY - BOOK AU - Arman, Vassighi AU - Manoj, Sachdev ED - Anantha, Chandrakasan / Series editor TI - Thermal and Power Management of Integrated Circuits. Chapter 4: Thermal and Electrothermal Modeling TS - Chapter 4: Thermal and Electrothermal Modeling T3 - Integrated Circuits and Systems PB - Springer Netherlands PY - 2006 SP - 188 SN - 9780387297491 DO - 10.1007/0-387-29749-9_4 UR - https://m2.mtmt.hu/api/publication/23892245 ID - 23892245 N1 - pp 83-118 LA - English DB - MTMT ER - TY - JOUR AU - Attar, S S AU - Yagoub, M C E AU - Mohammadi, F TI - Simulation of Electro-Thermal Effects in Device and Circuit JF - WSEAS TRANSACTIONS ON CIRCUITS AND SYSTEMS J2 - WSEAS TRANS CIRCUITS SYSTEMS VL - 5 PY - 2006 IS - 7 SP - 926 EP - 930 PG - 5 SN - 1109-2734 UR - https://m2.mtmt.hu/api/publication/23892189 ID - 23892189 N1 - 13892208 sz. közlemény utánközlése. LA - English DB - MTMT ER - TY - CONF AU - ATTAR, S SHARIFIAN AU - YAGOUB, M C E AU - MOHAMMADI, F TI - Simulation of Electro-Thermal Effects in Device and Circuit T2 - Proceedings of the 10th WSEAS International Conference on CIRCUITS PY - 2006 SP - 143 EP - 147 PG - 5 UR - https://m2.mtmt.hu/api/publication/23892208 ID - 23892208 N1 - Utánközlése: 13892189 LA - English DB - MTMT ER - TY - CHAP AU - B, Swahn AU - S, Hassoun TI - METS: A Metric for Electro-Thermal Sensitivity, and Its Application To FinFETs T2 - Proceedings of the 7th International Symposium on Quality Electronic Design (ISDEQ'06) SN - 0769525237 PY - 2006 SP - 121 EP - 126 PG - 6 DO - 10.1109/ISQED.2006.86 UR - https://m2.mtmt.hu/api/publication/23892200 ID - 23892200 LA - English DB - MTMT ER - TY - JOUR AU - Pedram, M AU - Nazarian, S TI - Thermal Modeling, Analysis, and Management in VLSI Circuits: Principles and Methods JF - PROCEEDINGS OF THE IEEE J2 - P IEEE VL - 94 PY - 2006 IS - 8 SP - 1487 EP - 1501 PG - 15 SN - 0018-9219 DO - 10.1109/JPROC.2006.879797 UR - https://m2.mtmt.hu/api/publication/23892249 ID - 23892249 N1 - Megjegyzés-23892169 doi:10.1109/JPROC.2006.879797 LA - English DB - MTMT ER - TY - CHAP AU - M, Ito AU - N, Hesegawa AU - R, Egawa AU - KI, Suzuki AU - T, Nakamura TI - An Adaptive-Grain Thermal Simulation Method to Evaluate Effects of Spatio-Temporal Analysis Granularity upon The Thermal Behavior of VLSIs T2 - Proceedings of the 11th International Workshop on THERMal INvestigations of ICs and Systems (THERMINIC'05) PB - TIMA Laboratory CY - Grenoble SN - 2916187014 PY - 2005 SP - 43 EP - 50 PG - 8 UR - https://m2.mtmt.hu/api/publication/26813208 ID - 26813208 N1 - http://documents.irevues.inist.fr/handle/2042/6432 LA - English DB - MTMT ER - TY - CHAP AU - R, Egawa AU - M, Ito AU - N, Hasegawa AU - T, Nakamura AU - K, Suzuki TI - Temperature Gradient Alleviating Method for Arithmetic Units T2 - Proceedings of the 11th International Workshop on THERMal INvestigations of ICs and Systems (THERMINIC'05) PB - TIMA Laboratory CY - Grenoble SN - 2916187014 PY - 2005 SP - 151 EP - 156 PG - 6 UR - https://m2.mtmt.hu/api/publication/23892198 ID - 23892198 LA - English DB - MTMT ER - TY - CHAP AU - Sokolowska, E AU - Barszcz, M AU - Kaminska, B TI - TED thermo electrical designer: a new physical design verification tool T2 - 6th International Symposium on Quality Electronic Design, Proceedings SN - 0769523013 PY - 2005 SP - 164 EP - 168 PG - 5 DO - 10.1109/ISQED.2005.119 UR - https://m2.mtmt.hu/api/publication/23892216 ID - 23892216 LA - English DB - MTMT ER - TY - CHAP AU - ITO, Mutsuo AU - EGAWA, Ryusuke AU - SANO, Kentaro AU - SUZUKI, Ken-Ichi AU - NAKAMURA, Tadao TI - Simulating fine-grain thermal behaviors on VLSIs T2 - Proceedings of the 10th International Workshop on THERMal INvestigations of ICs and Systems (THERMINIC'04) SN - 2848130369 PY - 2004 SP - 63 EP - 68 PG - 6 UR - https://m2.mtmt.hu/api/publication/23892238 ID - 23892238 LA - English DB - MTMT ER - TY - CHAP AU - K, Skadron AU - M R, Stan AU - W, Huang AU - Zhijian, Lu AU - K, Sankaranarayanan AU - J, Lach ED - Ernst, LJ ED - Zhang, GQ ED - Rodgers, P ED - Leger, OD TI - A computer-architecture approach to thermal management in computer systems: opportunities and challenges T2 - Proceedings of the 5th International Conference on Thermal and Mechanical Simulation and Experiments in Microelectronics and Microsystems (EuroSimE'04) SN - 0780384202 PY - 2004 SP - 415 EP - 422 PG - 8 DO - 10.1109/ESIME.2004.1304072 UR - https://m2.mtmt.hu/api/publication/23932522 ID - 23932522 LA - English DB - MTMT ER - TY - CONF AU - Sani, R Nassif TI - Model to Hardware Closure for nm Generation Technologies T2 - Proceedings of the 12th Workshop on Synthesis And System Integration of MIxed Technologies (SASIMI'04) PY - 2004 SP - 15 EP - 20 PG - 6 UR - https://m2.mtmt.hu/api/publication/23892204 ID - 23892204 LA - English DB - MTMT ER - TY - CHAP AU - Székely, Vladimir AU - Poppe, András AU - Hajas, G ED - Ernst, LJ ED - Zhang, GQ ED - Rodgers, P ED - Leger, OD TI - Electro-thermal Transistor Models in the Sissi Electro-thermal IC Simulator T2 - Proceedings of the 5th International Conference on Thermal and Mechanical Simulation and Experiments in Microelectronics and Microsystems (EuroSimE'04) PB - IEEE Press CY - Bruxelles SN - 0780384202 PY - 2004 SP - 105 EP - 112 PG - 8 DO - 10.1109/esime.2004.1304029 UR - https://m2.mtmt.hu/api/publication/2607107 ID - 2607107 LA - English DB - MTMT ER - TY - JOUR AU - Chiueh, Herming AU - Draper, Jeffrey AU - Choma, John TI - A dynamic thermal management circuit for system-on-chip designs JF - ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING J2 - ANALOG INTEGR CIRC S VL - 36 PY - 2003 IS - 1-2 SP - 175 EP - 181 PG - 7 SN - 0925-1030 DO - 10.1023/A:1024430504653 UR - https://m2.mtmt.hu/api/publication/23892835 ID - 23892835 LA - English DB - MTMT ER - TY - JOUR AU - Codecasa, L AU - D'Amore, D AU - Maffezzoni, P TI - An Arnoldi based thermal network reduction method for electro-thermal analysis JF - IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES J2 - IEEE T COMPON PACK T VL - 26 PY - 2003 IS - 1 SP - 186 EP - 192 PG - 7 SN - 1521-3331 DO - 10.1109/TCAPT.2002.808005 UR - https://m2.mtmt.hu/api/publication/23892191 ID - 23892191 LA - English DB - MTMT ER - TY - CHAP AU - Hoon, Lee J AU - Cho, B H TI - Large time-scale electro-thermal simulation for loss and thermal management of power MOSFET T2 - Proceedings of the 34th IEEE Annual Power Electronics Specialist Conference (PESC'03) SN - 0780377540 PY - 2003 SP - 112 EP - 117 PG - 6 UR - https://m2.mtmt.hu/api/publication/23892192 ID - 23892192 N1 - Vol. 1. LA - English DB - MTMT ER - TY - GEN AU - Kevin, Skadron AU - Mircea, R Stan' AU - Wei, Huang AU - Sivakumar, Velusamy AU - Karthik, Sankaranarayanan AU - David, Tarjan TI - Temperature-Aware Microarchitecture: Extended Discussion and Results PY - 2003 UR - https://m2.mtmt.hu/api/publication/23892203 ID - 23892203 LA - English DB - MTMT ER - TY - CHAP AU - Kerecsen Istvánné Rencz, Márta AU - Székely, Vladimir AU - Poppe, András ED - Wehn, N ED - Verkest, D TI - A fast algorithm for the layout based electro-thermal simulation T2 - Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE'03) PB - IEEE Computer Society Press CY - Los Alamitos (CA) SN - 0769518702 PY - 2003 SP - 1032 EP - 1037 PG - 6 DO - 10.1109/DATE.2003.1253740 UR - https://m2.mtmt.hu/api/publication/2613617 ID - 2613617 AB - A new algorithm has been developed for the layout based direct electro-thermal simulation of integrated circuits. The advantage of the direct electro-thermal simulation over simulator coupling is, that very fast changes can also be considered, the drawback is that the thermal nodes are added to the number of nodes of the network to be simulated. The novelties of our method are the modeling and the solution of the thermal structure. This paper presents the algorithm of the time constant spectrum based FOSTER chain matrix thermal modeling, and the new algorithm of the coupled electro-thermal solution, where parts of the network, which represent the thermal behavior, are not computed in all steps of the iteration. This speeded up algorithm works both in the time-, and in the frequency domain. A simulation example demonstrates a typical application: the prediction of how the layout arrangement and the packaging of an analogue integrated circuit influence the electrical parameters. LA - English DB - MTMT ER - TY - CHAP AU - Kerecsen Istvánné Rencz, Márta AU - Székely, Vladimir AU - Poppe, András AU - K, Torki AU - B, Courtois ED - IEEE, null TI - Electro-thermal simulation for the prediction of chip operation within the package T2 - Proceedings of the 19th IEEE Semiconductor Thermal Measurement and Management Symposium (SEMI-THERM'03) PB - IEEE Press CY - New York, New York SN - 0780377931 T3 - Proceedings IEEE Semiconductor Thermal Measurement and Management Symposium, ISSN 1065-2221 PY - 2003 SP - 168 EP - 175 PG - 8 DO - 10.1109/STHERM.2003.1194357 UR - https://m2.mtmt.hu/api/publication/2613619 ID - 2613619 LA - English DB - MTMT ER - TY - CHAP AU - Kerecsen Istvánné Rencz, Márta AU - Székely, Vladimir AU - Poppe, András AU - B, Courtois ED - Bergman, K ED - Courtois, B ED - Karam, JM ED - Korvink, J ED - Markus, K ED - Michel, B TI - Electro-thermal simulation of MEMS elements T2 - Proceedings of the Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP'03) PB - IEEE CY - New York, New York SN - 078037066X PY - 2003 SP - 15 EP - 20 PG - 6 DO - 10.1109/DTIP.2003.1287001 UR - https://m2.mtmt.hu/api/publication/2613621 ID - 2613621 LA - English DB - MTMT ER - TY - GEN AU - PULTRONICS, Inc TI - TED software tools for thermal evaluation of integrated circuits. White Paper Version 2.1 TS - White Paper Version 2.1 PY - 2003 PG - 29 UR - https://m2.mtmt.hu/api/publication/25401610 ID - 25401610 LA - English DB - MTMT ER - TY - CHAP AU - Kerecsen Istvánné Rencz, Márta AU - Székely, Vladimir AU - Poppe, András AU - Courtois, B ED - Laudon, M ED - Romanowicz, B TI - Algorithmic and Modeling Aspects in the Electro-thermal Simulation of Thermally Operated Microsystems T2 - Technical Proceedings of the 2003 Nanotechnology Conference and Trade Show (NANOTECH'03) PB - National Nanotechnology Infrastructure Network CY - Cambridge SN - 0972842217 PY - 2003 SP - 476 EP - 479 PG - 4 UR - https://m2.mtmt.hu/api/publication/2607072 ID - 2607072 AB - A new algorithm has been developed for the layout based electro-thermal simulation of integrated circuits and MEMS, using simultaneous iteration. The general advantage of this method over simulator coupling is that, in contrast with the case of simulator coupling, very fast changes can also be considered. The usual drawback is however, that the thermal nodes have to be added to the nodes of the electrical network, rendering usually huge networks to be simulated. The novelties of our method are the modeling and the solution of the thermal structure that results in fastened calculations. The novelty of the modeling is that the thermal impedances are represented with the discretised thermal time-constant spectrum. The novelty of the solution algorithm is that in our method pre-computed solutions are used for the representation of the linear thermal sub-network, effectively reducing the number of thermal nodes that are participating in the iteration. This fastened algorithm works both in the time-, and in the frequency domain. The paper will shortly summarize the algorithm of the time constant spectrum based thermal modeling and the new algorithm of the electro-thermal co-simulation. In order to verify the correctness of the simulated electrical and thermal values, the simulated results will be compared with the measured results of a realised electro-thermal converter. LA - English DB - MTMT ER - TY - CHAP AU - S, Koziel AU - W, Szezesniak ED - V, Székely TI - High level synthesis with adaptive evolutionary algorithm for solving reliability and thermal problems in reconfigurable microelectronic systems T2 - Proceedings of the 9th International Workshop on THERMal INvestigations of ICs and Systems (THERMINIC'03) PB - BME Elektronikus Eszközök Tanszék CY - Aix-en-Provence SN - 2848130202 PY - 2003 SP - 79 EP - 84 PG - 6 UR - https://m2.mtmt.hu/api/publication/23892170 ID - 23892170 N1 - Source: PublEx LA - English DB - MTMT ER - TY - JOUR AU - Stan, MR AU - Skadron, K AU - Barcella, M AU - Huang, W AU - Sankaranarayanan, K AU - Velusamy, S TI - HotSpot: a dynamic compact thermal model at the processor-architecture level JF - MICROELECTRONICS JOURNAL J2 - MICROELECTRON J VL - 34 PY - 2003 IS - 12 SP - 1153 EP - 1165 PG - 13 SN - 0026-2692 DO - 10.1016/S0026-2692(03)00206-4 UR - https://m2.mtmt.hu/api/publication/23892558 ID - 23892558 LA - English DB - MTMT ER - TY - CONF AU - Kevin, Skadron AU - Mircea, Stan AU - Marco, Barcella AU - Amar, Dwarka AU - Wei, Huang AU - Yingmin, Li AU - Yong, Ma AU - Amit, Naidu AU - Dharmesh, Parikh AU - Paolo, Re AU - Garrett, Rose AU - Karthik, Sankaranarayanan AU - Ram, Suryanarayan AU - Sivakumar, Velusamy AU - Hao, Zhang AU - Yan, Zhang TI - HotSpot: techniques for modeling thermal effects at the processor-architecture level, T2 - Proceedings of the 8th International Workshop on THERMal INvestigations of ICs and Systems (THERMINIC'02) PB - IEEE PY - 2002 SP - 169 EP - 172 PG - 4 UR - https://m2.mtmt.hu/api/publication/23932521 ID - 23932521 N1 - Source: PublEx LA - English DB - MTMT ER - TY - CONF AU - K, Torki AU - F, Ciontu TI - IC thermal map from digital and thermal simulations T2 - Proceedings of the 8th International Workshop on THERMal INvestigations of ICs and Systems (THERMINIC'02) PB - IEEE PY - 2002 SP - 303 EP - 308 PG - 6 UR - https://m2.mtmt.hu/api/publication/23932449 ID - 23932449 N1 - Source: PublEx LA - English DB - MTMT ER - TY - JOUR AU - Altet, J AU - Rubio, A AU - Schaub, E AU - Dilhaire, S AU - Claeys, W TI - Thermal coupling in integrated circuits: application to thermal testing JF - IEEE JOURNAL OF SOLID-STATE CIRCUITS J2 - IEEE J SOLID-ST CIRC VL - 36 PY - 2001 IS - 1 SP - 81 EP - 91 PG - 11 SN - 1402070764 SN - 0018-9200 DO - 10.1109/4.896232 UR - https://m2.mtmt.hu/api/publication/23892085 ID - 23892085 N1 - doi:10.1109/4.896232 LA - English DB - MTMT ER - TY - JOUR AU - Batty, W AU - Christoffersen, CE AU - Panks, AJ AU - David, S AU - Snowden, CM AU - Steer, MB TI - Electrothremal CAD of power devices and circuits with fully physical time-dependent compact thermal modeling of complex nonlinear 3D systems JF - IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES J2 - IEEE T COMPON PACK T VL - 24 PY - 2001 IS - 4 SP - 566 EP - 590 PG - 25 SN - 1521-3331 DO - 10.1109/6144.974944 UR - https://m2.mtmt.hu/api/publication/24029418 ID - 24029418 N1 - :doi 10.1109/6144.974944 LA - English DB - MTMT ER - TY - CHAP AU - Batty, W AU - Christoffersen, CE AU - David, S AU - Panks, AJ AU - Johnson, RG AU - Snowden, CM AU - Steer, MB ED - IEEE, null TI - Fully physical time-dependent compact thermal modelling of complex non linear 3-dimensional systems for device and circuit level electro-thermal CAD T2 - Proceedings of the 17th IEEE Semiconductor Thermal Measurement and Management Symposium (SEMI-THERM'01) PB - IEEE Press CY - New York, New York SN - 0780366492 T3 - Proceedings IEEE Semiconductor Thermal Measurement and Management Symposium, ISSN 1065-2221 PY - 2001 SP - 71 EP - 84 PG - 14 DO - 10.1109/STHERM.2001.915149 UR - https://m2.mtmt.hu/api/publication/24029549 ID - 24029549 LA - English DB - MTMT ER - TY - JOUR AU - Chan-Su, Yun AU - Malberti, P AU - Ciappa, M AU - Fichtner, W TI - Thermal component model for electrothermal analysis of IGBT module systems JF - IEEE TRANSACTIONS ON ADVANCED PACKAGING J2 - IEEE T ADV PACKAGING VL - 24 PY - 2001 IS - 3 SP - 401 EP - 406 PG - 6 SN - 1521-3323 DO - 10.1109/6040.938309 UR - https://m2.mtmt.hu/api/publication/23892193 ID - 23892193 LA - English DB - MTMT ER - TY - CHAP AU - Chiueh, H AU - Draper, J AU - Choma, J TI - A dynamic thermal management circuit for system-on-chip designs T2 - ICECS 2001: 8TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS I-III, CONFERENCE PROCEEDINGS SN - 0780370570 PY - 2001 SP - 577 EP - 580 PG - 4 DO - 10.1109/ICECS.2001.957542 UR - https://m2.mtmt.hu/api/publication/23892222 ID - 23892222 LA - English DB - MTMT ER - TY - CHAP AU - Igic, P M AU - Mawby, P A AU - Towers, M S AU - Batcup, S ED - IEEE, null TI - Dynamic electro-thermal physically based compact models of the power devices for device and circuit simulations T2 - Proceedings of the 17th IEEE Semiconductor Thermal Measurement and Management Symposium (SEMI-THERM'01) PB - IEEE Press CY - New York, New York SN - 0780366492 T3 - Proceedings IEEE Semiconductor Thermal Measurement and Management Symposium, ISSN 1065-2221 PY - 2001 SP - 35 EP - 42 PG - 8 DO - 10.1109/STHERM.2001.915142 UR - https://m2.mtmt.hu/api/publication/23892174 ID - 23892174 N1 - Source: PublEx LA - English DB - MTMT ER - TY - JOUR AU - Jakovljevic, M AU - Fotiu, PA AU - Mrcarica, Z AU - Litovski, V AU - Detter, H TI - Electro-thermal simulation of microsystems with mixed abstraction modelling JF - MICROELECTRONICS RELIABILITY J2 - MICROELECTRON RELIAB VL - 41 PY - 2001 IS - 6 SP - 823 EP - 835 PG - 13 SN - 0026-2714 DO - 10.1016/S0026-2714(01)00024-5 UR - https://m2.mtmt.hu/api/publication/23892176 ID - 23892176 N1 - Source: PublEx Megjegyzés-23902222 doi:10.1016/S0026-2714(01)00024-5 LA - English DB - MTMT ER - TY - JOUR AU - Mawby, PA AU - Igic, PM AU - Towers, MS TI - Physically based compact device models for circuit modelling applications JF - MICROELECTRONICS JOURNAL J2 - MICROELECTRON J VL - 32 PY - 2001 IS - 5-6 SP - 433 EP - 447 PG - 15 SN - 0026-2692 DO - 10.1016/S0026-2692(01)00013-1 UR - https://m2.mtmt.hu/api/publication/23892175 ID - 23892175 N1 - Source: PublEx LA - English DB - MTMT ER - TY - CHAP AU - Sani, R Nassif TI - Modeling and forecasting of manufacturing variations T2 - Proceedings of the ASP-DAC 2001 Asia and South Pacific Design Automation Conference SN - 0780366344 PY - 2001 SP - 145 EP - 150 PG - 6 DO - 10.1145/370155.370308 UR - https://m2.mtmt.hu/api/publication/23892199 ID - 23892199 LA - English DB - MTMT ER - TY - JOUR AU - Szczesniak, W AU - Voss, B AU - Theisen, M AU - Becker, J AU - Glesner, M TI - Influence of high-level synthesis on average and peak temperatures of CMOS circuits JF - MICROELECTRONICS JOURNAL J2 - MICROELECTRON J VL - 32 PY - 2001 IS - 10-11 SP - 855 EP - 862 PG - 8 SN - 0026-2692 DO - 10.1016/S0026-2692(01)00073-8 UR - https://m2.mtmt.hu/api/publication/23892177 ID - 23892177 LA - English DB - MTMT ER - TY - CONF AU - Ching-Han, Tsai AU - Sung-Mo, Kang TI - Substrate thermal model reduction for efficient transient electrothermal simulation T2 - Proceedings of the Southwest Symposium on Mixed-Signal Design (SSMSD'00) PY - 2000 SP - 185 EP - 190 PG - 6 DO - 10.1109/SSMSD.2000.836471 UR - https://m2.mtmt.hu/api/publication/23892195 ID - 23892195 N1 - doi:10.1109/SSMSD.2000.836471 LA - English DB - MTMT ER - TY - JOUR AU - Noren, KV AU - Tarakji, A TI - Thermal macromodelling of integrated circuits JF - INTERNATIONAL JOURNAL OF ELECTRONICS J2 - INT J ELECTRON VL - 87 PY - 2000 IS - 8 SP - 941 EP - 959 PG - 19 SN - 0020-7217 DO - 10.1080/002072100404604 UR - https://m2.mtmt.hu/api/publication/23892183 ID - 23892183 N1 - Source: PublEx LA - English DB - MTMT ER - TY - CHAP AU - K O, Petrojanc AU - I A, Kharitonov AU - P, Maltcev AU - N I, Rjabov AU - L N, Kravtchenko AU - A N, Sapelnikov ED - Anon, null TI - High-speed digital GaAs ICs electro-thermal simulation with PSPICE T2 - Proceedings of the 18th International Workshop on THERMal INvestigation of ICs and Systems (THERMINIC'99) PB - TIMA Laboratory CY - Grenoble SN - 2913329322 PY - 1999 SP - 103 EP - 106 PG - 4 UR - https://m2.mtmt.hu/api/publication/23892253 ID - 23892253 N1 - Source: PublEx LA - English DB - MTMT ER - TY - JOUR AU - Kerecsen Istvánné Rencz, Márta AU - Székely, Vladimir AU - A, Páhi AU - Poppe, András TI - Algorithmic and practical questions of electro-thermal circuit simulation JF - PROCEEDINGS OF SPIE - THE INTERNATIONAL SOCIETY FOR OPTICAL ENGINEERING J2 - PROCEEDINGS OF SPIE VL - 3893 PY - 1999 SP - 178 EP - 187 PG - 10 SN - 0277-786X DO - 10.1117/12.368423 UR - https://m2.mtmt.hu/api/publication/2613574 ID - 2613574 AB - In recent years great attention has been paid to the thermal issues in electronics design on system, board, package and chip level, including thermal and electro-thermal simulation of integrated circuits and MCM-s, or even integrated microsystems. In this paper we address some algorithmic issues regarding the method of simultaneous iteration. With the node reduction algorithm outlined here electro-thermal simulation of large problems becomes feasible. Besides this algorithmic innovation we provide a specification for a modular, platform independent electro-thermal simulator. LA - English DB - MTMT ER - TY - JOUR AU - Nakamura, T TI - Introducing cool chips JF - IEEE MICRO J2 - IEEE MICRO VL - 19 PY - 1999 IS - 4 SP - 9 EP - 10 PG - 2 SN - 0272-1732 DO - 10.1109/MM.1999.782562 UR - https://m2.mtmt.hu/api/publication/23892194 ID - 23892194 LA - English DB - MTMT ER - TY - CHAP AU - Kerecsen Istvánné Rencz, Márta AU - Székely, Vladimir AU - Páhi, A AU - Poppe, András ED - Carothers, Jo Dale TI - An alternative method for electro-thermal circuit simulation T2 - Proceedings of the IEEE 1999 Southwest Symposium on Mixed-Signal Design (SSMSD '99) PB - IEEE Press CY - New York, New York SN - 0780355105 PY - 1999 SP - 117 EP - 122 PG - 6 DO - 10.1109/SSMSD.1999.768603 UR - https://m2.mtmt.hu/api/publication/2613575 ID - 2613575 LA - English DB - MTMT ER - TY - JOUR AU - Székely, Vladimir AU - Kerecsen Istvánné Rencz, Márta AU - Courtois, B TI - A Step Forward in the Transient Thermal Characterization of Chips and Packages JF - MICROELECTRONICS RELIABILITY J2 - MICROELECTRON RELIAB VL - 39 PY - 1999 IS - 1 SP - 89 EP - 96 PG - 8 SN - 0026-2714 DO - 10.1016/S0026-2714(98)00198-X UR - https://m2.mtmt.hu/api/publication/2607045 ID - 2607045 AB - Generating compact dynamic thermal models is a key issue in the thermal characterization of packages. A further but related problem is the modeling of the thermal coupling between chip locations, for the use in electro-thermal circuit simulators. The paper presents a measurement based method which provides a way to solve both problems. A thermal benchmark chip has been designed and realized, to facilitate thermal transient measurements. The developed evaluation method provides the compact thermal multiport model of the IC chip including package effects, for the accurate electro-thermal simulation of the ICs. The evaluation method is also suitable to generate the compact thermal model of the package. (C) 1999 Elsevier Science Ltd. All rights reserved. LA - English DB - MTMT ER - TY - JOUR AU - Székely, Vladimir AU - Pahi, A AU - Poppe, András AU - Kerecsen Istvánné Rencz, Márta TI - Electro-Thermal Simulation with the SISSI Package JF - ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING J2 - ANALOG INTEGR CIRC S VL - 21 PY - 1999 IS - 1 SP - 21 EP - 31 PG - 11 SN - 0925-1030 DO - 10.1023/A:1008371625945 UR - https://m2.mtmt.hu/api/publication/2606987 ID - 2606987 AB - In this paper a brief overview of the electro-thermal simulation based on the method of simultaneous iteration is given, through the example of the SISSI (Simulator for Integrated Structures by Simultaneous Iteration) package. The modular approach used for the layout-based electro-thermal netlist generation is described. This approach allows an easy implementation of package model libraries. The capabilities of SISSI are introduced by simulation examples where in most cases the results are compared to measurement results. LA - English DB - MTMT ER - TY - CHAP AU - A, Páhi AU - V, Székely TI - Efficient thermal simulators: SUNRED and QuickTHERM T2 - Proceedings of the 1st IEEE International Workshop on Design, Test and Application (WDTA'98) SN - 9531840091 PY - 1998 SP - 85 EP - 88 PG - 4 UR - https://m2.mtmt.hu/api/publication/23892186 ID - 23892186 N1 - Source: PublEx LA - English DB - MTMT ER - TY - CHAP AU - Hajas, G AU - Lipták-Fegó, L ED - TIMA, Laboratory TI - Characterization of submicron bulk and SOI MOS transistors for electro-thermal and logi-thermal simulation T2 - Proceedings of the 4th International Workshop on THERMal INvestigations of ICs and Microstructures (THERMINIC'98) PB - TIMA Laboratory CY - Grenoble SN - 2913329012 PY - 1998 SP - 31 EP - 34 PG - 4 UR - https://m2.mtmt.hu/api/publication/23892185 ID - 23892185 N1 - Source: PublEx LA - English DB - MTMT ER - TY - JOUR AU - Mawby, P TI - Compact Electrothermal Models for Power Electronics JF - INSTITUTION OF ELECTRICAL ENGINEERS. COLLOQUIUM J2 - IEE VL - 1998 PY - 1998 IS - 486 SP - 3/1 EP - 3/4 SN - 0963-3308 DO - 10.1049/ic:19980894 UR - https://m2.mtmt.hu/api/publication/23892232 ID - 23892232 LA - English DB - MTMT ER - TY - JOUR AU - Székely, Vladimir AU - Kerecsen Istvánné Rencz, Márta AU - Courtois, B TI - Tracing the Thermal Behavior of ICs JF - IEEE DESIGN & TEST OF COMPUTERS J2 - IEEE DES TEST COMPUT VL - 15 PY - 1998 IS - 2 SP - 14 EP - 21 PG - 8 SN - 0740-7475 DO - 10.1109/54.679204 UR - https://m2.mtmt.hu/api/publication/2606986 ID - 2606986 AB - Today's increased power and packaging densities demand designer's attention to the effects of heat on ICs. Here, the authors review thermal and electrothermal simulation and measurement methods, thermal package characterization, and the concept and techniques of design for thermal testability. LA - English DB - MTMT ER - TY - THES AU - Csendes, Alpár TI - IC csipek és mikrostruktúrák termikus vizsgálata PY - 1997 UR - https://m2.mtmt.hu/api/publication/24129245 ID - 24129245 N1 - PhD értekezés BME Villamosmérnöki és Informatikai Kar, Elektronikus Eszközök Tanszéke, Budapest Source: PublEx LA - Hungarian DB - MTMT ER -