@inproceedings{MTMT:3411746,
	title = {Application of bit-serial arithmetic units for FPGA implementation of convolutional neural networks},
	url = {https://m2.mtmt.hu/api/publication/3411746},
	author = {Csordás, Gábor András and Fehér, Béla and Kovácsházy, Tamás},
	booktitle = {Proceedings of the 19th International Carpathian Control Conference (ICCC 2018)},
	doi = {10.1109/CarpathianCC.2018.8399649},
	unique-id = {3411746},
	keywords = {Computer vision; delays; Machine vision; FPGA; Field programmable gate arrays; Convolution; Code generation; FPGA implementation; Distributed arithmetic; Cyber-physical systems; Python; Real-time systems; Convolutional neural networks; Convolutional codes; Runtime; Adders; feedforward neural nets; Verilog; Hardware design languages; Verilog code generation; Python code; inference type; standard FPGA design tools; CNN convolutional layer; bit-serial multipliers; bit-serial implementation; bit-serial arithmetic units; hardware description languages; electronic engineering computing},
	year = {2018},
	pages = {322-327},
	orcid-numbers = {Kovácsházy, Tamás/0000-0001-5424-1588}
}