TY - JOUR AU - Kaarthik, RS AU - Gopakumar, K AU - Cecati, C AU - Nagy, István TI - Timing Calculations for a General N-Level Dodecagonal Space Vector Structure Using Only Reference Phase Voltages JF - IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS J2 - IEEE T IND ELECTRON VL - 63 PY - 2016 IS - 3 SP - 1395 EP - 1403 PG - 9 SN - 0278-0046 DO - 10.1109/TIE.2015.2495283 UR - https://m2.mtmt.hu/api/publication/3121329 ID - 3121329 AB - Multilevel inverters with dodecagonal (12-sided polygon) voltage space vector (SV) structures have advantages like extension of linear modulation range, elimination of fifth and seventh harmonics in phase voltages and currents for the full modulation range including extreme 12-step operation, reduced device voltage ratings, lesser dv/dt stresses on devices and motor phase windings resulting in lower EMI/EMC problems, and lower switching frequency-making it more suitable for high-power drive applications. This paper proposes a simple method to obtain pulsewidth modulation (PWM) timings for a dodecagonal voltage SV structure using only sampled reference voltages. In addition to this, a carrier-based method for obtaining the PWM timings for a general N-level dodecagonal structure is proposed in this paper for the first time. The algorithm outputs the triangle information and the PWM timing values which can be set as the compare values for any carrier-based hardware PWM module to obtain SV PWM like switching sequences. The proposed method eliminates the need for angle estimation, computation of modulation indices, and iterative search algorithms that are typical in multilevel dodecagonal SV systems. The proposed PWM scheme was implemented on a five-level dodecagonal SV structure. Exhaustive simulation and experimental results for steady-state and transient conditions are presented to validate the proposed method. LA - English DB - MTMT ER - TY - JOUR AU - Járdán, Rafael Kálmán AU - Stumpf, Péter Pál AU - Varga, Zoltán AU - Nagy, István TI - Novel Solutions for High-Speed Self-Excited Induction Generators JF - IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS J2 - IEEE T IND ELECTRON VL - 63 PY - 2016 IS - 4 SP - 2124 EP - 2132 PG - 9 SN - 0278-0046 DO - 10.1109/TIE.2015.2506149 UR - https://m2.mtmt.hu/api/publication/2993742 ID - 2993742 LA - English DB - MTMT ER - TY - CHAP AU - Kaarthik, RS AU - Gopakumar, K AU - Cecati, C AU - Nagy, István TI - Timing calculations for three level dodecagonal space vector structure from reference phase voltages T2 - 41st Annual Conference of the IEEE Industrial Electronics Society, IECON 2015 PB - Institute of Electrical and Electronics Engineers (IEEE) CY - Piscataway (NJ) SN - 9781479917624 PY - 2015 SP - 19 EP - 24 PG - 6 DO - 10.1109/IECON.2015.7392070 UR - https://m2.mtmt.hu/api/publication/3128423 ID - 3128423 LA - English DB - MTMT ER - TY - CHAP AU - Rahul, SA AU - Kaarthik, RS AU - Gopakumar, K AU - Rajeevan, PP AU - Franquelo, LG AU - Leon, JI AU - Nagy, István ED - IEEE, null TI - A Hybrid Seven Level Inverter Topology with a Single DC Supply and Reduced Switch Count T2 - 2015 17th European Conference on Power Electronics and Applications (EPE'15 ECCE-Europe) PB - IEEE CY - Piscataway (NJ) SN - 9789075815238 PY - 2015 PG - 10 DO - 10.1109/EPE.2015.7309051 UR - https://m2.mtmt.hu/api/publication/3111880 ID - 3111880 AB - In this paper, a new three-phase hybrid seven level inverter topology with a single DC supply is proposed for the first time. The proposed inverter is realized by cascading two three level flying capacitor inverters with a half bridge module. The inverter topology is having multiple switching state redundancies for each of the pole voltage levels. By using these switching state redundancies, capacitor charging can be controlled in every PWM switching cycle. This feature is advantageous for reducing the capacitor sizing. Another advantage of the proposed inverter is that the charge balancing of each capacitor can be controlled irrespective of modulation index and load power factor. A hysteresis controller based capacitor charge control algorithm is implemented for the proposed inverter. Furthermore, the proposed topology uses lesser number of semiconductor devices, capacitors and DC power supplies compared to conventional seven level inverter topologies. The proposed topology is tested with open loop V/f control scheme in an induction motor drive. Inverter is tested for entire modulation range, and experimental results for steady-state operation are presented for various fundamental frequencies. Experimental results showing the effectiveness of capacitor charge control for both steady state and transient operating conditions are presented. LA - English DB - MTMT ER - TY - JOUR AU - Kaarthik, RS AU - Gopakumar, K AU - Cecati, C AU - Nagy, István TI - A Voltage Space Vector Diagram Formed by Nineteen Concentric Dodecagons for Medium-Voltage Induction Motor Drive JF - IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS J2 - IEEE T IND ELECTRON VL - 62 PY - 2015 IS - 11 SP - 6748 EP - 6755 PG - 8 SN - 0278-0046 DO - 10.1109/TIE.2015.2436876 UR - https://m2.mtmt.hu/api/publication/3000558 ID - 3000558 AB - In this paper, a multilevel dodecagonal voltage space vector structure with nineteen concentric dodecagons is proposed for the first time. This space vector structure is achieved by cascading two sets of asymmetric three-level inverters with isolated H-bridges on either side of an open-end winding induction motor. The dodecagonal structure is made possible by proper selection of dc link voltages and switching states of the inverters. The proposed scheme retains all the advantages of multilevel topologies as well as the advantages of dodecagonal voltage space vector structure. In addition to that, a generic and simple method for calculation of pulsewidth modulation timings using only sampled reference values (v(alpha) and v(beta)) is proposed. This enables the scheme to be used for any closed-loop application such as vector control. In addition, a new method of switching technique is proposed, which ensures minimum switching while eliminating the fifth-and seventh-order harmonics and suppressing the eleventh and thirteenth harmonics, eliminating the need for bulky filters. The motor phase voltage is a 24-stepped wave-form for the entire modulation range thereby reducing the number of switchings of the individual inverter modules. Experimental results for steady-state operation, transient operation, including start-up have been presented and the results of fast Fourier transform analysis is also presented for validating the proposed concept. LA - English DB - MTMT ER - TY - CHAP AU - Kurucsó, B. AU - Peschka, A. AU - Stumpf, Péter Pál AU - Nagy, István AU - Vajk, István ED - H, Bulent Ertan TI - State Space Control of Quadratic Boost Converter using LQR and LQG approaches T2 - ACEMP-OPTIM-Electromotion joint conference: 2015 Intl Aegean Conference on Electrical Machines & Power Electronics (ACEMP), 2015 Intl Conference on Optimization of Electrical & Electronic Equipment (OPTIM) & 2015 Intl Symposium on Advanced Electromechanical Motion Systems (ELECTROMOTION) PB - IEEE CY - Piscataway (NJ) SN - 9781467372404 PY - 2015 SP - 642 EP - 648 PG - 7 DO - 10.1109/OPTIM.2015.7427003 UR - https://m2.mtmt.hu/api/publication/2995719 ID - 2995719 LA - English DB - MTMT ER - TY - CHAP AU - Stumpf, Péter Pál AU - Berei, József AU - Nagy, István AU - Vajk, István TI - Dynamics of DFIG controlled by Rotor Side Converter in wind energy T2 - 2015 5TH INTERNATIONAL YOUTH CONFERENCE ON ENERGY (IYCE) PB - IEEE CY - New York, New York CY - Piscataway (NJ) SN - 1467371726 PY - 2015 PG - 8 DO - 10.1109/IYCE.2015.7180797 UR - https://m2.mtmt.hu/api/publication/2991474 ID - 2991474 LA - English DB - MTMT ER - TY - JOUR AU - Stumpf, Péter Pál AU - Nagy, István AU - Vajk, István TI - Control of Power Flow Between the Wind Generator and Network JF - IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS J2 - IEEE T IND APPL VL - 51 PY - 2015 IS - 6 SP - 4699 EP - 4708 PG - 10 SN - 0093-9994 DO - 10.1109/TIA.2015.2445821 UR - https://m2.mtmt.hu/api/publication/2972564 ID - 2972564 LA - English DB - MTMT ER - TY - CHAP AU - Járdán, Rafael Kálmán AU - Varga, Zoltán AU - Stumpf, Péter Pál AU - Nagy, István AU - Christian, Endisch AU - Sipos, Péter AU - Simon, Miklós TI - Development of a Dedicated Laboratory System for Measurement of Iron Losses in High Speed PMSM T2 - 2015 IEEE International Conference on Industrial Technology, ICIT 2015 PB - IEEE CY - New York, New York CY - Piscataway (NJ) SN - 9781479978007 PY - 2015 SP - 708 EP - 713 PG - 6 DO - 10.1109/ICIT.2015.7125181 UR - https://m2.mtmt.hu/api/publication/2870106 ID - 2870106 LA - English DB - MTMT ER - TY - JOUR AU - Rakos, Balázs AU - Nagy, István TI - Simulation of Basic, Protein-Based Logic Gates JF - ADVANCED MATERIALS RESEARCH J2 - ADV MATER RES VL - 1117 PY - 2014 SP - 132 EP - 135 PG - 4 SN - 1022-6680 DO - 10.4028/www.scientific.net/AMR.1117.132 UR - https://m2.mtmt.hu/api/publication/3148166 ID - 3148166 LA - English DB - MTMT ER -