The development of the space-air-ground integration has put higher demands on satellite
network. It needs to support high-bandwidth, large-capacity and various quality of
service guarantees. However, the satellite onboard switching is facing the problem
of resource constraints and special requirements of hardware complexity and scheduling
efficiency. For this, this paper proposes a novel memory architecture for high-bandwidth
onboard switching fabric. To reduce hardware complexity, multiplexer is used in the
input side to merge k input ports into one internal bus, while the output demultiplexer
splits an internal bus into k output links. Shared memory architecture is adopted
in the input module to improve the memory efficiency, and a buffered crossbar is used
to interconnect the input modules to the output modules. A discrete-time queuing model
is formulated, and an iterative approach is used to quantitatively analyze the performance
of the proposed architecture. The throughput and delay are calculated under different
switch size, input load, and buffer capacity. The numerical results can serve as a
guidance on deciding the required buffer size and appropriate speedup ratio. This
work is validated by both simulations and FPGA implementations. Synthesize result
show that using the state-of-the-art Xilinx VU13P FPGA, a switching fabric with 48
ports can be implemented and the peak throughput of the proposed architecture can
reach 480 Gbps. Compared with existing combined input-crosspoint queuing, the proposed
architecture can significantly reduce the packet delay and the memory resource cost.
