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          <label>1. Timar, A., Bognar, G., Poppe, A., Rencz, M., Electro-thermal cosimulation of ICs with runtime back-annotation capability Thermal Investigations of ICs and Systems (THERMINIC), 2010 16th International Workshop On, Barcelona, Spain, Oct. 2010, pp. 1-6</label>
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          <label>3. Pable, S., Hasan, M., Ultra-low-power signaling challenges for subthreshold global interconnects (2012) Integration, the VLSI Journal, 45 (2), pp. 186-196. , http://www.sciencedirect.com/science/article/pii/S0167926011000770, [Online]. Available</label>
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          <label>4. Rebaud, B., Belleville, M., Beigné, E., Bernard, C., Robert, M., Maurine, P., Azemard, N., Timing slack monitoring under process and environmental variations: Application to a DSP performance optimization (2011) Microelectronics Journal, 42 (5), pp. 718-732. , http://www.sciencedirect.com/science/article/pii/S0026269211000292, [Online]. Available</label>
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          <label>5. Lin, S., Kim, Y.-B., Lombardi, F., Design and analysis of a 32nm PVT tolerant CMOS SRAM cell for low leakage and high stability (2010) Integration, the VLSI Journal, 43 (2), pp. 176-187. , http://www.sciencedirect.com/science/article/pii/S0167926010000040, [Online]. Available</label>
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          <label>6. Kumar, R., Kursun, V., Reversed temperature-dependent propagation delay characteristics in nanometer CMOS circuits (2006) Circuits and Systems II: Express Briefs, IEEE Transactions on, 53 (10), pp. 1078-1082. , oct</label>
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          <label>7. Sánchez-Azqueta, C., Celma, S., Aznar, F., A 0.18 μm CMOS ring VCO for clock and data recovery applications (2011) Microelectronics Reliability, 51 (12), pp. 2351-2356. , http://www.sciencedirect.com/science/article/pii/S0026271411001697, [Online]. Available</label>
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          <label>8. Wang, J., Gong, N., Hou, L., Peng, X., Sridhar, R., Wu, W., Leakage current, active power, and delay analysis of dynamic dual vt cmos circuits under P-V-T fluctuations (2011) Microelectronics Reliability, 51 (9-11), pp. 1498-1502. , http://www.sciencedirect.com/science/article/pii/S0026271411002010, proceedings of the 22th European Symposium on the RELIABILITY OF ELECTRON DEVICES, FAILURE PHYSICS AND ANALYSIS. [Online]. Available</label>
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          <label>9. Winther, A., Liu, W., Nannarelli, A., Vrudhula, S., Temperature dependent wire delay estimation in floorplanning (2011) NORCHIP, pp. 1-4. , nov. 2011</label>
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          <label>10. Golda, A., Kos, A., Temperature influence on power consumption and time delay Digital System Design, 2003. Proceedings. Euromicro Symposium On, Sept. 2003, pp. 378-382</label>
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&lt;div class=&quot;lastModified&quot;&gt;Utolsó módosítás: 2022.01.06. 14:40 Sövény Emese (BME admin 5)
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	&lt;pre class=&quot;comment&quot; style=&quot;margin-top: 0; margin-bottom: 0;&quot;&gt;&lt;u&gt;Megjegyzés&lt;/u&gt;: Befoglaló mű WoS és MTMT megnevezése nem azonos. Az MTMT-ben 1995 óta standardizált konferenciamegnevezéssel lett a befoglaló mű rögzítve.&lt;/pre&gt;
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