In today's digital electronic integrated circuits device heating is one of the most
critical issues. Overheating can cause failures in functionality and device malfunction.
In certain circumstances overheating of ICs can cause physical destruction of the
device itself. This paper introduces a solution to determine cell and gate heating
curves across the standard cell IC's surface. The presented methodology and toolset
is tightly integrated into standardized logic simulator engines thus providing digital
circuit designers a lowlevel,
cell-resolution temperature distribution map during logic simulations. Actual temperatures
of each consisting cell of the design can be monitored throughout the whole logic
simulation. By being able to monitor temperatures of digital cells during initial
simulations, it allows us to detect hot-spots and overheating caused malfunctions
far before manufacture. By using the spatial location and temperature magnitude of
hot-spots acquired from the presented methodology, place and route (P&R) tools can
be driven to change cell placement and routing in order to avoid heating caused failures.
Additionally,
cooling solutions can be developed using the simulated temperature maps of the IC's
surface. This paper also presents various aspects of power characterization methods
which were used throughout the experiments.
