Due to the ever increasing power density in today's VLSI designs, the need for considering
thermal effects during the design phase is increasing. IC designers and CAD vendors
seem to agree, that certain physical phenomena, such as thermal problems, need to
be considered even during high level simulations. This paper describes a new approach
for considering thermal issues during gate level logic simulation of digital ICs.
This type of simulation is called logi-thermal simulation, since a standard logic
simulator is coupled to a thermal simulator within an IC design framework. The logi-thermal
simulation is performed on fully placed and routed designs. Both the dissipation and
the temperature dependent timing parameters of the gates are calculated and taken
into consideration. An experimental logi-thermal simulation system has been developed
for a 5 V, 1.0 µm CMOS process, in form of extending Verilog with new gate models
and with a fast thermal simulation option. A benchmark chip has been investigated.
Comparing measurement and simulation results suggests that logi-thermal simulation
can be a useful verification tool in the final design phase of digital IC.