Thermal effects are rapidly gaining importance in nanometer CMOS technologies. Increased
power density, coupled with spatio-temporal variability of chip workloads, causes
on-die temperature non-uniformities. The assumption of a uniform temperature for the
delay and power analysis of a large CMOS circuit produces inaccurate results. For
this reason, significant design margins are taken to ensure safe operation. To improve
design quality, we need precise localization of hotspots at detailed spatial resolution
which is very computationally intensive. Consequently, thermal analysis needs to be
done at multiple levels of granularity using a versatile thermal floorplan. We propose
MiMAPT, an approach for analyzing delay, power and temperature in digital circuits.
MiMAPT integrates seamlessly into major industrial Front-end and Back-end chip design
flows. It accounts for temperature non-uniformities and self-heating while performing
analysis. Thermal analysis is done at register-transfer (RT) and then gate-level considering
non-regular shapes of on-die units with multiple scales of resolution and speed. To
demonstrate the capability of MiMAPT in temperature variation aware delay/power estimation,
a widely used IP block is chosen and four different chips are implemented using 65
nm and 40 nm (LVT, HVT) technology nodes. Different temperature patterns are then
applied to the design. Accuracy improvements of up to 28% for static power and 16%
for minimum clock period are reported in comparison with uniform averaged temperature
assumption. Evaluating the ability of MiMAPT in multi-scale thermal analysis, a speed-up
of 98x is reported compared to fine-grained method, while keeping false negatives
at zero and the error of temperature estimation below 0.05 degrees C. (C) 2014 Elsevier
B.V. All rights reserved.
